From fd06aa7c076f397b307ddd638a2666f4090ee2b1 Mon Sep 17 00:00:00 2001
From: Dan Gohman <gohman@apple.com>
Date: Mon, 7 Sep 2009 23:47:14 +0000
Subject: [PATCH] Fix a thinko: When lowering fneg with xor, bitcast the
 operands from floating-point to integer first, and bitcast the result back to
 floating-point. Previously, this test was passing by falling back to
 SelectionDAG lowering. The resulting code isn't as nice, but it's correct and
 CodeGen now stays on the fast path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81171 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/FastISel.cpp | 21 +++++++++++++++++----
 test/CodeGen/X86/fast-isel-fneg.ll    |  6 +++---
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index f0c70861843..8550ea9813d 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -615,12 +615,25 @@ FastISel::SelectFNeg(User *I) {
   unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
   if (OpReg == 0) return false;
 
-  // Twiddle the sign bit with xor.
+  // Bitcast the value to integer, twiddle the sign bit with xor,
+  // and then bitcast it back to floating-point.
   EVT VT = TLI.getValueType(I->getType());
   if (VT.getSizeInBits() > 64) return false;
-  unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISD::XOR, OpReg,
-                                    UINT64_C(1) << (VT.getSizeInBits()-1),
-                                    VT.getSimpleVT());
+  EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
+
+  unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
+                               ISD::BIT_CONVERT, OpReg);
+  if (IntReg == 0)
+    return false;
+
+  unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
+                                       UINT64_C(1) << (VT.getSizeInBits()-1),
+                                       IntVT.getSimpleVT());
+  if (IntResultReg == 0)
+    return false;
+
+  unsigned ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
+                                  ISD::BIT_CONVERT, IntResultReg);
   if (ResultReg == 0)
     return false;
 
diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll
index 41b288ba1de..02c5e4e2299 100644
--- a/test/CodeGen/X86/fast-isel-fneg.ll
+++ b/test/CodeGen/X86/fast-isel-fneg.ll
@@ -1,14 +1,14 @@
-; RUN: llvm-as < %s | llc -fast-isel -march=x86-64 | FileCheck %s
+; RUN: llvm-as < %s | llc -fast-isel -fast-isel-abort -march=x86-64 | FileCheck %s
 
 ; CHECK: doo:
-; CHECK: xorpd
+; CHECK: xor
 define double @doo(double %x) nounwind {
   %y = fsub double -0.0, %x
   ret double %y
 }
 
 ; CHECK: foo:
-; CHECK: xorps
+; CHECK: xor
 define float @foo(float %x) nounwind {
   %y = fsub float -0.0, %x
   ret float %y
-- 
2.34.1