From f760d95bdeb40620a8de81aa5055387fcf531ce1 Mon Sep 17 00:00:00 2001 From: James Y Knight Date: Wed, 19 Aug 2015 15:59:49 +0000 Subject: [PATCH] [Sparc] Rename LoadASR and StoreASR from r245360 to *ASI, as was intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245450 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcInstrInfo.td | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 02b3f080c2f..b39e16796e3 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -283,9 +283,9 @@ multiclass Load Op3Val, SDPatternOperator OpNode, [(set Ty:$dst, (OpNode ADDRri:$addr))]>; } -// TODO: Instructions of the LoadASR class are currently asm only; hooking up +// TODO: Instructions of the LoadASI class are currently asm only; hooking up // CodeGen's address spaces to use these is a future task. -class LoadASR Op3Val, SDPatternOperator OpNode, +class LoadASI Op3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), !strconcat(OpcStr, "a [$addr] $asi, $dst"), @@ -295,7 +295,7 @@ class LoadASR Op3Val, SDPatternOperator OpNode, multiclass LoadA Op3Val, bits<6> LoadAOp3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : Load { - def Arr : LoadASR; + def Arr : LoadASI; } // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. @@ -311,9 +311,9 @@ multiclass Store Op3Val, SDPatternOperator OpNode, [(OpNode Ty:$rd, ADDRri:$addr)]>; } -// TODO: Instructions of the StoreASR class are currently asm only; hooking up +// TODO: Instructions of the StoreASI class are currently asm only; hooking up // CodeGen's address spaces to use these is a future task. -class StoreASR Op3Val, +class StoreASI Op3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), !strconcat(OpcStr, "a $rd, [$addr] $asi"), @@ -322,7 +322,7 @@ class StoreASR Op3Val, multiclass StoreA Op3Val, bits<6> StoreAOp3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : Store { - def Arr : StoreASR; + def Arr : StoreASI; } //===----------------------------------------------------------------------===// @@ -422,12 +422,12 @@ let DecoderMethod = "DecodeLoadIntPair" in // Section B.2 - Load Floating-point Instructions, p. 92 let DecoderMethod = "DecodeLoadFP" in { defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>; - def LDFArr : LoadASR<"ld", 0b110000, load, FPRegs, f32>, + def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32>, Requires<[HasV9]>; } let DecoderMethod = "DecodeLoadDFP" in { defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>; - def LDDFArr : LoadASR<"ldd", 0b110011, load, DFPRegs, f64>, + def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>, Requires<[HasV9]>; } let DecoderMethod = "DecodeLoadQFP" in @@ -447,12 +447,12 @@ let DecoderMethod = "DecodeStoreIntPair" in // Section B.5 - Store Floating-point Instructions, p. 97 let DecoderMethod = "DecodeStoreFP" in { defm STF : Store<"st", 0b100100, store, FPRegs, f32>; - def STFArr : StoreASR<"st", 0b110100, store, FPRegs, f32>, + def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>, Requires<[HasV9]>; } let DecoderMethod = "DecodeStoreDFP" in { defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>; - def STDFArr : StoreASR<"std", 0b110111, store, DFPRegs, f64>, + def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>, Requires<[HasV9]>; } let DecoderMethod = "DecodeStoreQFP" in -- 2.34.1