From f11ac42d01b99970f5335a78dd4277184c3a3c1f Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Thu, 21 Aug 2014 10:31:37 +0000 Subject: [PATCH] X86: Turn redundant if into an assertion. While there remove noop casts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216168 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index b2f2562f25a..00d1e5cd270 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1843,9 +1843,7 @@ X86TargetLowering::findRepresentativeClass(MVT VT) const{ default: return TargetLowering::findRepresentativeClass(VT); case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: - RRC = Subtarget->is64Bit() ? - (const TargetRegisterClass*)&X86::GR64RegClass : - (const TargetRegisterClass*)&X86::GR32RegClass; + RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass; break; case MVT::x86mmx: RRC = &X86::VR64RegClass; @@ -10669,12 +10667,12 @@ static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && isa(N2)) { unsigned Opc; - if (VT == MVT::v8i16) + if (VT == MVT::v8i16) { Opc = X86ISD::PINSRW; - else if (VT == MVT::v16i8) - Opc = X86ISD::PINSRB; - else + } else { + assert(VT == MVT::v16i8); Opc = X86ISD::PINSRB; + } // Transform it so it match pinsr{b,w} which expects a GR32 as its second // argument. -- 2.34.1