From eb1fef0ec148983cd97a761dc76101823cf81a34 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 5 Sep 2014 14:08:01 +0000 Subject: [PATCH] R600/SI: Fix bug in SIInstrInfo::legalizeOpWithMove() We must constrain the destination register class of legalized operands to a VGPR class or else the illegal operand may be folded back into the instruction by the register coalescer. This fixes a bug in add.ll that will be uncovered by future commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217249 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrInfo.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 11aaf45fe32..6875181a2e5 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -984,17 +984,18 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; const TargetRegisterClass *RC = RI.getRegClass(RCID); unsigned Opcode = AMDGPU::V_MOV_B32_e32; - if (MO.isReg()) { Opcode = AMDGPU::COPY; } else if (RI.isSGPRClass(RC)) { Opcode = AMDGPU::S_MOV_B32; - } else if (MO.isImm()) { - if (RC == &AMDGPU::VSrc_32RegClass) - Opcode = AMDGPU::S_MOV_B32; } const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); + if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) { + VRC = &AMDGPU::VReg_64RegClass; + } else { + VRC = &AMDGPU::VReg_32RegClass; + } unsigned Reg = MRI.createVirtualRegister(VRC); BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode), Reg).addOperand(MO); -- 2.34.1