From de246de95876149b4f4086819968686462a4fd09 Mon Sep 17 00:00:00 2001
From: "Arnaud A. de Grandmaison" <arnaud.degrandmaison@arm.com>
Date: Tue, 21 Oct 2014 20:47:22 +0000
Subject: [PATCH] [PBQP] Teach PassConfig to tell if the default register
 allocator is used.

This enables targets to adapt their pass pipeline to the register
allocator in use. For example, with the AArch64 backend, using PBQP
with the cortex-a57, the FPLoadBalancing pass is no longer necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220321 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/CodeGen/Passes.h               |  4 ++++
 lib/CodeGen/Passes.cpp                      |  6 ++++++
 lib/Target/AArch64/AArch64TargetMachine.cpp | 15 ++-------------
 lib/Target/AArch64/AArch64TargetMachine.h   |  4 ----
 test/CodeGen/AArch64/PBQP.ll                |  4 ++--
 5 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 31fba89c7ac..e45b3e0a1a3 100644
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -178,6 +178,10 @@ public:
   /// Return true if the optimized regalloc pipeline is enabled.
   bool getOptimizeRegAlloc() const;
 
+  /// Return true if the default global register allocator is in use and
+  /// has not be overriden on the command line with '-regalloc=...'
+  bool usingDefaultRegAlloc() const;
+
   /// Add common target configurable passes that perform LLVM IR to IR
   /// transforms following machine independent optimization.
   virtual void addIRPasses();
diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp
index 53869b1544d..46f912e62d6 100644
--- a/lib/CodeGen/Passes.cpp
+++ b/lib/CodeGen/Passes.cpp
@@ -690,6 +690,12 @@ FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
   return createTargetRegisterAllocator(Optimized);
 }
 
+/// Return true if the default global register allocator is in use and
+/// has not be overriden on the command line with '-regalloc=...'
+bool TargetPassConfig::usingDefaultRegAlloc() const {
+  return RegAlloc == &useDefaultRegisterAllocator;
+}
+
 /// Add the minimum set of target-independent passes that are required for
 /// register allocation. No coalescing or scheduling.
 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp
index fbe0b9bc4e2..439bde101d9 100644
--- a/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -75,11 +75,6 @@ EnableCondOpt("aarch64-condopt",
               cl::desc("Enable the condition optimizer pass"),
               cl::init(true), cl::Hidden);
 
-static cl::opt<bool>
-EnablePBQP("aarch64-pbqp", cl::Hidden,
-           cl::desc("Use PBQP register allocator (experimental)"),
-           cl::init(false));
-
 static cl::opt<bool>
 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
                 cl::desc("Work around Cortex-A53 erratum 835769"),
@@ -101,14 +96,8 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
                                            CodeGenOpt::Level OL,
                                            bool LittleEndian)
     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
-      Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian),
-      usingPBQP(false) {
+      Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
   initAsmInfo();
-
-  if (EnablePBQP && Subtarget.isCortexA57() && OL != CodeGenOpt::None) {
-    usingPBQP = true;
-    RegisterRegAlloc::setDefault(createDefaultPBQPRegisterAllocator);
-  }
 }
 
 const AArch64Subtarget *
@@ -263,7 +252,7 @@ bool AArch64PassConfig::addPostRegAlloc() {
     addPass(createAArch64DeadRegisterDefinitions());
   if (TM->getOptLevel() != CodeGenOpt::None &&
       TM->getSubtarget<AArch64Subtarget>().isCortexA57() &&
-      !static_cast<const AArch64TargetMachine *>(TM)->isPBQPUsed())
+      usingDefaultRegAlloc())
     // Improve performance for some FP/SIMD code for A57.
     addPass(createAArch64A57FPLoadBalancing());
   return true;
diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h
index 7bf40ae165b..3e571c9d9eb 100644
--- a/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/lib/Target/AArch64/AArch64TargetMachine.h
@@ -43,12 +43,8 @@ public:
   /// \brief Register AArch64 analysis passes with a pass manager.
   void addAnalysisPasses(PassManagerBase &PM) override;
 
-  /// \brief Query if the PBQP register allocator is being used
-  bool isPBQPUsed() const { return usingPBQP; }
-
 private:
   bool isLittle;
-  bool usingPBQP;
 };
 
 // AArch64leTargetMachine - AArch64 little endian target machine.
diff --git a/test/CodeGen/AArch64/PBQP.ll b/test/CodeGen/AArch64/PBQP.ll
index 491998e1e30..675a2ca60dd 100644
--- a/test/CodeGen/AArch64/PBQP.ll
+++ b/test/CodeGen/AArch64/PBQP.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a57 -aarch64-pbqp -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a57 -regalloc=pbqp -pbqp-coalescing -o - %s | FileCheck %s
 
 define i32 @foo(i32 %a) {
 ; CHECK-LABEL: foo:
 ; CHECK: bl bar
-; CHECK-NEXT: bl baz
+; CHECK: bl baz
   %call = call i32 @bar(i32 %a)
   %call1 = call i32 @baz(i32 %call)
   ret i32 %call1
-- 
2.34.1