From dac237e18209b697a8ba122d0ddd9cad4dfba1f8 Mon Sep 17 00:00:00 2001 From: Torok Edwin Date: Wed, 8 Jul 2009 20:53:28 +0000 Subject: [PATCH] Implement changes from Chris's feedback. Finish converting lib/Target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineCodeEmitter.h | 2 - include/llvm/CodeGen/SelectionDAGISel.h | 2 - include/llvm/Support/ErrorHandling.h | 6 +- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 1 + lib/Target/ARM/ARMCodeEmitter.cpp | 15 ++-- lib/Target/ARM/ARMISelDAGToDAG.cpp | 3 + lib/Target/ARM/ARMJITInfo.cpp | 4 +- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 6 +- lib/Target/ARM/Thumb1RegisterInfo.cpp | 1 + lib/Target/ARM/Thumb2RegisterInfo.cpp | 3 +- lib/Target/Alpha/AlphaCodeEmitter.cpp | 8 +- lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 2 + lib/Target/Alpha/AlphaISelLowering.cpp | 1 + lib/Target/Alpha/AlphaInstrInfo.cpp | 8 +- lib/Target/Alpha/AlphaJITInfo.cpp | 1 + .../Alpha/AsmPrinter/AlphaAsmPrinter.cpp | 2 +- lib/Target/CBackend/CBackend.cpp | 54 ++++++++----- .../CellSPU/AsmPrinter/SPUAsmPrinter.cpp | 7 +- lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 36 ++++----- lib/Target/CellSPU/SPUISelLowering.cpp | 77 +++++++++++-------- lib/Target/CellSPU/SPUInstrInfo.cpp | 19 ++--- lib/Target/CellSPU/SPURegisterInfo.cpp | 17 ++-- lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp | 6 +- lib/Target/IA64/IA64ISelDAGToDAG.cpp | 2 + lib/Target/IA64/IA64ISelLowering.cpp | 1 + lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 2 + lib/Target/MSP430/MSP430ISelLowering.cpp | 10 +-- lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp | 8 +- lib/Target/Mips/MipsISelDAGToDAG.cpp | 2 + lib/Target/PIC16/PIC16ISelDAGToDAG.cpp | 2 + .../PowerPC/AsmPrinter/PPCAsmPrinter.cpp | 19 ++--- lib/Target/PowerPC/PPCCodeEmitter.cpp | 6 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 8 +- lib/Target/PowerPC/PPCISelLowering.cpp | 9 ++- lib/Target/PowerPC/PPCInstrInfo.cpp | 14 ++-- lib/Target/PowerPC/PPCJITInfo.cpp | 8 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 5 +- .../Sparc/AsmPrinter/SparcAsmPrinter.cpp | 8 +- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 2 + .../X86/AsmPrinter/X86ATTInstPrinter.cpp | 2 +- lib/Target/X86/X86CodeEmitter.cpp | 9 +-- lib/Target/X86/X86ISelDAGToDAG.cpp | 2 + lib/Target/X86/X86ISelLowering.cpp | 3 +- lib/Target/XCore/XCoreAsmPrinter.cpp | 8 +- lib/Target/XCore/XCoreISelDAGToDAG.cpp | 2 + lib/Target/XCore/XCoreISelLowering.cpp | 18 +++-- lib/Target/XCore/XCoreRegisterInfo.cpp | 10 +-- lib/VMCore/AsmWriter.cpp | 3 +- lib/VMCore/Globals.cpp | 1 + lib/VMCore/Instructions.cpp | 1 + lib/VMCore/Type.cpp | 4 +- lib/VMCore/Value.cpp | 5 +- lib/VMCore/Verifier.cpp | 4 +- 53 files changed, 263 insertions(+), 196 deletions(-) diff --git a/include/llvm/CodeGen/MachineCodeEmitter.h b/include/llvm/CodeGen/MachineCodeEmitter.h index 987661597f7..ece416c78db 100644 --- a/include/llvm/CodeGen/MachineCodeEmitter.h +++ b/include/llvm/CodeGen/MachineCodeEmitter.h @@ -18,8 +18,6 @@ #define LLVM_CODEGEN_MACHINECODEEMITTER_H #include "llvm/Support/DataTypes.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" namespace llvm { diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index b98636aa6e4..d2c0dc420f8 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -19,8 +19,6 @@ #include "llvm/Pass.h" #include "llvm/Constant.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" namespace llvm { class FastISel; diff --git a/include/llvm/Support/ErrorHandling.h b/include/llvm/Support/ErrorHandling.h index 758d9243c04..c7e4297f00c 100644 --- a/include/llvm/Support/ErrorHandling.h +++ b/include/llvm/Support/ErrorHandling.h @@ -49,7 +49,11 @@ namespace llvm { void llvm_unreachable(void) NORETURN; } -#define LLVM_UNREACHABLE(msg) do { assert(0 && msg); llvm_unreachable(); } while(0) +#ifndef NDEBUG +#define LLVM_UNREACHABLE(msg) do {cerr<::getMachineOpValue(const MachineInstr &MI, else if (MO.isMBB()) emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); else { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "ERROR: Unknown type of MachineOperand: " << MO; - llvm_report_error(Msg.str()); +#ifndef NDEBUG + cerr << MO; +#endif + llvm_unreachable(); } return 0; } @@ -588,7 +588,7 @@ void Emitter::emitPseudoInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; switch (Opcode) { default: - llvm_report_error("ARMCodeEmitter::emitPseudoInstruction");//FIXME: + LLVM_UNREACHABLE("ARMCodeEmitter::emitPseudoInstruction");//FIXME: case TargetInstrInfo::INLINEASM: { // We allow inline assembler nodes with empty bodies - they can // implicitly define registers, which is ok for JIT. @@ -1119,8 +1119,9 @@ template void Emitter::emitBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); - if (TID.Opcode == ARM::TPsoft) - llvm_report_error("ARM::TPsoft FIXME"); // FIXME + if (TID.Opcode == ARM::TPsoft) { + LLVM_UNREACHABLE("ARM::TPsoft FIXME"); // FIXME + } // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 6d7e41cc35f..71a63059002 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -30,6 +30,9 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" + using namespace llvm; static const unsigned arm_dsubreg_0 = 5; diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp index bc28919817c..c9e04c9506f 100644 --- a/lib/Target/ARM/ARMJITInfo.cpp +++ b/lib/Target/ARM/ARMJITInfo.cpp @@ -123,12 +123,12 @@ extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) { // ldr pc, [pc,#-4] // if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) { - llvm_report_error("ERROR: Unable to mark stub writable"); + LLVM_UNREACHABLE("ERROR: Unable to mark stub writable"); } *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4] *(intptr_t *)(StubAddr+4) = NewVal; if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) { - llvm_report_error("ERROR: Unable to mark stub executable"); + LLVM_UNREACHABLE("ERROR: Unable to mark stub executable"); } } diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index d9e21b8e077..67c42580465 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -120,7 +120,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) { case ARM::FSTD: NumFSTMGened++; return ARM::FSTMD; - default: llvm_report_error("Unhandled opcode!"); + default: LLVM_UNREACHABLE("Unhandled opcode!"); } return 0; } @@ -442,7 +442,7 @@ static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) { case ARM::FLDD: return ARM::FLDMD; case ARM::FSTS: return ARM::FSTMS; case ARM::FSTD: return ARM::FSTMD; - default: llvm_report_error("Unhandled opcode!"); + default: LLVM_UNREACHABLE("Unhandled opcode!"); } return 0; } @@ -455,7 +455,7 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) { case ARM::FLDD: return ARM::FLDMD; case ARM::FSTS: return ARM::FSTMS; case ARM::FSTD: return ARM::FSTMD; - default: llvm_report_error("Unhandled opcode!"); + default: LLVM_UNREACHABLE("Unhandled opcode!"); } return 0; } diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 316f5ad22c2..125b4612535 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -32,6 +32,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; static cl::opt diff --git a/lib/Target/ARM/Thumb2RegisterInfo.cpp b/lib/Target/ARM/Thumb2RegisterInfo.cpp index bca205a039d..f5a8b82478b 100644 --- a/lib/Target/ARM/Thumb2RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb2RegisterInfo.cpp @@ -455,8 +455,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; } default: - llvm_report_error("Unsupported addressing mode!"); - break; + LLVM_UNREACHABLE("Unsupported addressing mode!"); } Offset += InstrOffs * Scale; diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp index 56f515e5492..9a7c5a4f86b 100644 --- a/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -235,10 +235,10 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), Alpha::reloc_bsr, MO.getMBB())); } else { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "ERROR: Unknown type of MachineOperand: " << MO; - llvm_report_error(Msg.str()); +#ifndef NDEBUG + cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; +#endif + llvm_unreachable(); } return rv; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index a774850461c..6fa05fc1086 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -28,7 +28,9 @@ #include "llvm/Intrinsics.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include using namespace llvm; diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 176255c93d6..49fb262b5a8 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -25,6 +25,7 @@ #include "llvm/Intrinsics.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; /// AddLiveIn - This helper function adds the specified physical register to the diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 17a9bc2f689..62b5d4c3012 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -201,7 +201,7 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - llvm_report_error("Unhandled register class"); + LLVM_UNREACHABLE("Unhandled register class"); } void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::STQ; else - llvm_report_error("Unhandled register class"); + LLVM_UNREACHABLE("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); @@ -246,7 +246,7 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - llvm_report_error("Unhandled register class"); + LLVM_UNREACHABLE("Unhandled register class"); } void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -261,7 +261,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::LDQ; else - llvm_report_error("Unhandled register class"); + LLVM_UNREACHABLE("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); diff --git a/lib/Target/Alpha/AlphaJITInfo.cpp b/lib/Target/Alpha/AlphaJITInfo.cpp index 6e9579a2a7e..c62ab75523f 100644 --- a/lib/Target/Alpha/AlphaJITInfo.cpp +++ b/lib/Target/Alpha/AlphaJITInfo.cpp @@ -18,6 +18,7 @@ #include "llvm/CodeGen/JITCodeEmitter.h" #include "llvm/Config/alloca.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include using namespace llvm; diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp index feab490c64b..11f177dd279 100644 --- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp @@ -101,7 +101,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { return; case MachineOperand::MO_Immediate: - llvm_report_error("printOp() does not handle immediate values"); + LLVM_UNREACHABLE("printOp() does not handle immediate values"); return; case MachineOperand::MO_MachineBasicBlock: diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index 294c6d35bea..70495d07268 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -35,6 +35,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/Support/CallSite.h" #include "llvm/Support/CFG.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/InstVisitor.h" #include "llvm/Support/Mangler.h" @@ -321,8 +322,10 @@ namespace { void visitExtractValueInst(ExtractValueInst &I); void visitInstruction(Instruction &I) { +#ifndef NDEBUG cerr << "C Writer does not know about " << I; - abort(); +#endif + llvm_unreachable(); } void outputLValue(Instruction *I) { @@ -505,8 +508,10 @@ CWriter::printSimpleType(raw_ostream &Out, const Type *Ty, bool isSigned, } default: +#ifndef NDEBUG cerr << "Unknown primitive type: " << *Ty << "\n"; - abort(); +#endif + llvm_unreachable(); } } @@ -550,8 +555,10 @@ CWriter::printSimpleType(std::ostream &Out, const Type *Ty, bool isSigned, } default: +#ifndef NDEBUG cerr << "Unknown primitive type: " << *Ty << "\n"; - abort(); +#endif + llvm_unreachable(); } } @@ -652,8 +659,7 @@ raw_ostream &CWriter::printType(raw_ostream &Out, const Type *Ty, return Out << TyName << ' ' << NameSoFar; } default: - assert(0 && "Unhandled case in getTypeProps!"); - abort(); + LLVM_UNREACHABLE("Unhandled case in getTypeProps!"); } return Out; @@ -756,8 +762,7 @@ std::ostream &CWriter::printType(std::ostream &Out, const Type *Ty, return Out << TyName << ' ' << NameSoFar; } default: - assert(0 && "Unhandled case in getTypeProps!"); - abort(); + LLVM_UNREACHABLE("Unhandled case in getTypeProps!"); } return Out; @@ -1104,9 +1109,11 @@ void CWriter::printConstant(Constant *CPV, bool Static) { return; } default: +#ifndef NDEBUG cerr << "CWriter Error: Unhandled constant expression: " << *CE << "\n"; - abort(); +#endif + llvm_unreachable(); } } else if (isa(CPV) && CPV->getType()->isSingleValueType()) { Out << "(("; @@ -1312,8 +1319,10 @@ void CWriter::printConstant(Constant *CPV, bool Static) { } // FALL THROUGH default: +#ifndef NDEBUG cerr << "Unknown constant type: " << *CPV << "\n"; - abort(); +#endif + llvm_unreachable(); } } @@ -1456,10 +1465,9 @@ void CWriter::writeInstComputationInline(Instruction &I) { const Type *Ty = I.getType(); if (Ty->isInteger() && (Ty!=Type::Int1Ty && Ty!=Type::Int8Ty && Ty!=Type::Int16Ty && Ty!=Type::Int32Ty && Ty!=Type::Int64Ty)) { - cerr << "The C backend does not currently support integer " - << "types of widths other than 1, 8, 16, 32, 64.\n"; - cerr << "This is being tracked as PR 4158.\n"; - abort(); + llvm_report_error("The C backend does not currently support integer " + "types of widths other than 1, 8, 16, 32, 64.\n" + "This is being tracked as PR 4158."); } // If this is a non-trivial bool computation, make sure to truncate down to @@ -2663,7 +2671,11 @@ void CWriter::visitBinaryOperator(Instruction &I) { case Instruction::Shl : Out << " << "; break; case Instruction::LShr: case Instruction::AShr: Out << " >> "; break; - default: cerr << "Invalid operator type!" << I; abort(); + default: +#ifndef NDEBUG + cerr << "Invalid operator type!" << I; +#endif + llvm_unreachable(); } writeOperandWithCast(I.getOperand(1), I.getOpcode()); @@ -2700,7 +2712,11 @@ void CWriter::visitICmpInst(ICmpInst &I) { case ICmpInst::ICMP_SLT: Out << " < "; break; case ICmpInst::ICMP_UGT: case ICmpInst::ICMP_SGT: Out << " > "; break; - default: cerr << "Invalid icmp predicate!" << I; abort(); + default: +#ifndef NDEBUG + cerr << "Invalid icmp predicate!" << I; +#endif + llvm_unreachable(); } writeOperandWithCast(I.getOperand(1), I); @@ -3020,10 +3036,12 @@ bool CWriter::visitBuiltinCall(CallInst &I, Intrinsic::ID ID, Out << ", "; // Output the last argument to the enclosing function. if (I.getParent()->getParent()->arg_empty()) { - cerr << "The C backend does not currently support zero " + std::string msg; + raw_string_ostream Msg(msg); + Msg << "The C backend does not currently support zero " << "argument varargs functions, such as '" - << I.getParent()->getParent()->getName() << "'!\n"; - abort(); + << I.getParent()->getParent()->getName() << "'!"; + llvm_report_error(Msg.str()); } writeOperand(--I.getParent()->getParent()->arg_end()); Out << ')'; diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 2847d0b8393..4d516438def 100644 --- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -30,6 +30,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetAsmInfo.h" @@ -319,8 +320,7 @@ namespace { void SPUAsmPrinter::printOp(const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_Immediate: - cerr << "printOp() does not handle immediate values\n"; - abort(); + llvm_report_error("printOp() does not handle immediate values"); return; case MachineOperand::MO_MachineBasicBlock: @@ -573,8 +573,7 @@ void LinuxAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::InternalLinkage: break; default: - cerr << "Unknown linkage type!"; - abort(); + llvm_report_error("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 779d75d0218..f9801d53494 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -31,8 +31,10 @@ #include "llvm/GlobalValue.h" #include "llvm/Intrinsics.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -191,10 +193,11 @@ namespace { #ifndef NDEBUG if (retval == 0) { - cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for " - << VT.getMVTString() - << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for " + << VT.getMVTString(); + llvm_report_error(Msg.str()); } #endif @@ -437,16 +440,14 @@ SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base, case ISD::Constant: case ISD::ConstantPool: case ISD::GlobalAddress: - cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n"; - abort(); + llvm_report_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered."); /*NOTREACHED*/ case ISD::TargetConstant: case ISD::TargetGlobalAddress: case ISD::TargetJumpTable: - cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as " - << "A-form address.\n"; - abort(); + llvm_report_error("SPUSelectAFormAddr: Target Constant/Pool/Global " + "not wrapped as A-form address."); /*NOTREACHED*/ case SPUISD::AFormAddr: @@ -730,10 +731,8 @@ SPUDAGToDAGISel::Select(SDValue Op) { switch (Op0VT.getSimpleVT()) { default: - cerr << "CellSPU Select: Unhandled zero/any extend MVT\n"; - abort(); + llvm_report_error("CellSPU Select: Unhandled zero/any extend MVT"); /*NOTREACHED*/ - break; case MVT::i32: shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, CurDAG->getConstant(0x80808080, MVT::i32), @@ -900,10 +899,11 @@ SPUDAGToDAGISel::Select(SDValue Op) { const valtype_map_s *vtm = getValueTypeMapEntry(VT); if (vtm->ldresult_ins == 0) { - cerr << "LDRESULT for unsupported type: " - << VT.getMVTString() - << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "LDRESULT for unsupported type: " + << VT.getMVTString(); + llvm_report_error(Msg.str()); } Opc = vtm->ldresult_ins; @@ -1231,8 +1231,8 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, MVT OpVT, return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(emitBuildVector(i64vec), 0)); } else { - cerr << "SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec condition\n"; - abort(); + llvm_report_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec" + "condition"); } } diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index d8a77766bd5..78790073198 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -28,7 +28,9 @@ #include "llvm/Function.h" #include "llvm/Intrinsics.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetOptions.h" #include @@ -70,10 +72,11 @@ namespace { #ifndef NDEBUG if (retval == 0) { - cerr << "getValueTypeMapEntry returns NULL for " - << VT.getMVTString() - << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "getValueTypeMapEntry returns NULL for " + << VT.getMVTString(); + llvm_report_error(Msg.str()); } #endif @@ -665,11 +668,15 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { case ISD::POST_INC: case ISD::POST_DEC: case ISD::LAST_INDEXED_MODE: - cerr << "LowerLOAD: Got a LoadSDNode with an addr mode other than " + { + std::string msg; + raw_string_ostream Msg(msg); + Msg << "LowerLOAD: Got a LoadSDNode with an addr mode other than " "UNINDEXED\n"; - cerr << (unsigned) LN->getAddressingMode() << "\n"; - abort(); - /*NOTREACHED*/ + Msg << (unsigned) LN->getAddressingMode(); + llvm_report_error(Msg.str()); + /*NOTREACHED*/ + } } return SDValue(); @@ -830,11 +837,15 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { case ISD::POST_INC: case ISD::POST_DEC: case ISD::LAST_INDEXED_MODE: - cerr << "LowerLOAD: Got a LoadSDNode with an addr mode other than " + { + std::string msg; + raw_string_ostream Msg(msg); + Msg << "LowerLOAD: Got a LoadSDNode with an addr mode other than " "UNINDEXED\n"; - cerr << (unsigned) SN->getAddressingMode() << "\n"; - abort(); - /*NOTREACHED*/ + Msg << (unsigned) SN->getAddressingMode(); + llvm_report_error(Msg.str()); + /*NOTREACHED*/ + } } return SDValue(); @@ -920,9 +931,8 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo); } } else { - cerr << "LowerGlobalAddress: Relocation model other than static not " - << "supported.\n"; - abort(); + llvm_report_error("LowerGlobalAddress: Relocation model other than static" + "not supported."); /*NOTREACHED*/ } @@ -984,10 +994,11 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex) switch (ObjectVT.getSimpleVT()) { default: { - cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " - << ObjectVT.getMVTString() - << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "LowerFORMAL_ARGUMENTS Unhandled argument type: " + << ObjectVT.getMVTString(); + llvm_report_error(Msg.str()); } case MVT::i8: ArgRegClass = &SPU::R8CRegClass; @@ -1529,12 +1540,14 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { uint64_t SplatBits = APSplatBits.getZExtValue(); switch (VT.getSimpleVT()) { - default: - cerr << "CellSPU: Unhandled VT in LowerBUILD_VECTOR, VT = " - << VT.getMVTString() - << "\n"; - abort(); + default: { + std::string msg; + raw_string_ostream Msg(msg); + Msg << "CellSPU: Unhandled VT in LowerBUILD_VECTOR, VT = " + << VT.getMVTString(); + llvm_report_error(Msg.str()); /*NOTREACHED*/ + } case MVT::v4f32: { uint32_t Value32 = uint32_t(SplatBits); assert(SplatBitSize == 32 @@ -1948,8 +1961,8 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { // slot 0 across the vector MVT VecVT = N.getValueType(); if (!VecVT.isSimple() || !VecVT.isVector() || !VecVT.is128BitVector()) { - cerr << "LowerEXTRACT_VECTOR_ELT: Must have a simple, 128-bit vector type!\n"; - abort(); + llvm_report_error("LowerEXTRACT_VECTOR_ELT: Must have a simple, 128-bit" + "vector type!"); } // Make life easier by making sure the index is zero-extended to i32 @@ -1976,8 +1989,8 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { switch (VT.getSimpleVT()) { default: - cerr << "LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector type\n"; - abort(); + llvm_report_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector" + "type"); /*NOTREACHED*/ case MVT::i8: { SDValue factor = DAG.getConstant(0x00000000, MVT::i32); @@ -2458,9 +2471,7 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, case ISD::SETONE: compareOp = ISD::SETNE; break; default: - cerr << "CellSPU ISel Select: unimplemented f64 condition\n"; - abort(); - break; + llvm_report_error("CellSPU ISel Select: unimplemented f64 condition"); } SDValue result = @@ -2568,11 +2579,13 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) switch (Opc) { default: { +#ifndef NDEBUG cerr << "SPUTargetLowering::LowerOperation(): need to lower this!\n"; cerr << "Op.getOpcode() = " << Opc << "\n"; cerr << "*Op.getNode():\n"; Op.getNode()->dump(); - abort(); +#endif + llvm_unreachable(); } case ISD::LOAD: case ISD::EXTLOAD: diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index e629c8d31aa..eba1ca127c6 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -19,6 +19,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Support/Streams.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" using namespace llvm; @@ -313,8 +314,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } else if (RC == SPU::VECREGRegisterClass) { opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8; } else { - assert(0 && "Unknown regclass!"); - abort(); + LLVM_UNREACHABLE("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); @@ -328,8 +328,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { - cerr << "storeRegToAddr() invoked!\n"; - abort(); + llvm_report_error("storeRegToAddr() invoked!"); if (Addr[0].isFI()) { /* do what storeRegToStackSlot does here */ @@ -348,8 +347,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } else if (RC == SPU::VECREGRegisterClass) { /* Opc = PPC::STVX; */ } else { - assert(0 && "Unknown regclass!"); - abort(); + LLVM_UNREACHABLE("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) @@ -385,8 +383,7 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } else if (RC == SPU::VECREGRegisterClass) { opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8; } else { - assert(0 && "Unknown regclass in loadRegFromStackSlot!"); - abort(); + LLVM_UNREACHABLE("Unknown regclass in loadRegFromStackSlot!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); @@ -402,8 +399,7 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { - cerr << "loadRegToAddr() invoked!\n"; - abort(); + llvm_report_error("loadRegToAddr() invoked!"); if (Addr[0].isFI()) { /* do what loadRegFromStackSlot does here... */ @@ -424,8 +420,7 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } else if (RC == SPU::GPRCRegisterClass) { /* Opc = something else! */ } else { - assert(0 && "Unknown regclass!"); - abort(); + LLVM_UNREACHABLE("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index e031048e7cc..31c75eb6075 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -35,7 +35,9 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include @@ -176,8 +178,7 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) { case SPU::R126: return 126; case SPU::R127: return 127; default: - cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n"; - abort(); + llvm_report_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering"); } } @@ -485,8 +486,10 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const .addReg(SPU::R2) .addReg(SPU::R1); } else { - cerr << "Unhandled frame size: " << FrameSize << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Unhandled frame size: " << FrameSize; + llvm_report_error(Msg.str()); } if (hasDebugInfo) { @@ -577,8 +580,10 @@ SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const .addReg(SPU::R2) .addReg(SPU::R1); } else { - cerr << "Unhandled frame size: " << FrameSize << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Unhandled frame size: " << FrameSize; + llvm_report_error(Msg.str()); } } } diff --git a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp index 6faaf6c3c6a..111749e778d 100644 --- a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp +++ b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp @@ -318,11 +318,11 @@ void IA64AsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; case GlobalValue::GhostLinkage: - llvm_report_error("GhostLinkage cannot appear in IA64AsmPrinter!"); + LLVM_UNREACHABLE("GhostLinkage cannot appear in IA64AsmPrinter!"); case GlobalValue::DLLImportLinkage: - llvm_report_error("DLLImport linkage is not supported by this target!"); + LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - llvm_report_error("DLLExport linkage is not supported by this target!"); + LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); default: LLVM_UNREACHABLE("Unknown linkage type!"); } diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 9800c506ca9..739ae3115fb 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -26,7 +26,9 @@ #include "llvm/Intrinsics.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 3ef3dceac4d..1b661eba231 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Constants.h" #include "llvm/Function.h" using namespace llvm; diff --git a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index bf49ec0bff4..6dd3b2a2548 100644 --- a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -28,6 +28,8 @@ #include "llvm/Target/TargetLowering.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index 0fd96cc00eb..10d4457e791 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -193,11 +193,11 @@ SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op, switch (RegVT.getSimpleVT()) { default: { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "LowerFORMAL_ARGUMENTS Unhandled argument type: " - << RegVT.getSimpleVT(); - llvm_report_error(Msg.str()); +#ifndef NDEBUG + cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " + << RegVT.getSimpleVT() << "\n"; +#endif + llvm_unreachable(); } case MVT::i16: unsigned VReg = diff --git a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp index b2604e89e71..837e389a188 100644 --- a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp @@ -406,7 +406,7 @@ printOperand(const MachineInstr *MI, int opNum) break; default: - llvm_report_error(""); break; + LLVM_UNREACHABLE(""); } if (closeP) O << ")"; @@ -545,11 +545,11 @@ printModuleLevelGV(const GlobalVariable* GVar) { printSizeAndType = false; break; case GlobalValue::GhostLinkage: - llvm_report_error("Should not have any unmaterialized functions!"); + LLVM_UNREACHABLE("Should not have any unmaterialized functions!"); case GlobalValue::DLLImportLinkage: - llvm_report_error("DLLImport linkage is not supported by this target!"); + LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - llvm_report_error("DLLExport linkage is not supported by this target!"); + LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); default: LLVM_UNREACHABLE("Unknown linkage type!"); } diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 53de1bbea66..bce8e3d9d37 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -32,6 +32,8 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; //===----------------------------------------------------------------------===// diff --git a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp index 6c2b8ec9747..cc57d12c904 100644 --- a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp +++ b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp @@ -13,6 +13,8 @@ #define DEBUG_TYPE "pic16-isel" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "PIC16ISelDAGToDAG.h" #include "llvm/Support/Debug.h" diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp index 7f1673cf462..373a2efc008 100644 --- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp @@ -36,6 +36,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetAsmInfo.h" @@ -70,7 +71,7 @@ namespace { unsigned enumRegToMachineReg(unsigned enumReg) { switch (enumReg) { - default: assert(0 && "Unhandled register!"); break; + default: LLVM_UNREACHABLE("Unhandled register!"); case PPC::CR0: return 0; case PPC::CR1: return 1; case PPC::CR2: return 2; @@ -80,7 +81,7 @@ namespace { case PPC::CR6: return 6; case PPC::CR7: return 7; } - abort(); + llvm_unreachable(); } /// printInstruction - This method is automatically generated by tablegen @@ -348,9 +349,7 @@ namespace { void PPCAsmPrinter::printOp(const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_Immediate: - cerr << "printOp() does not handle immediate values\n"; - abort(); - return; + LLVM_UNREACHABLE("printOp() does not handle immediate values"); case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMBB()); @@ -552,9 +551,7 @@ void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) { if (printInstruction(MI)) return; // Printer was automatically generated - assert(0 && "Unhandled instruction in asm writer!"); - abort(); - return; + LLVM_UNREACHABLE("Unhandled instruction in asm writer!"); } /// runOnMachineFunction - This uses the printMachineInstruction() @@ -709,8 +706,7 @@ void PPCLinuxAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; default: - cerr << "Unknown linkage type!"; - abort(); + LLVM_UNREACHABLE("Unknown linkage type!"); } EmitAlignment(Align, GVar); @@ -940,8 +936,7 @@ void PPCDarwinAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; default: - cerr << "Unknown linkage type!"; - abort(); + LLVM_UNREACHABLE("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index eaa8269499d..c191f65888d 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -26,6 +26,8 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; @@ -263,8 +265,10 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), Reloc, MO.getMBB())); } else { +#ifndef NDEBUG cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; - abort(); +#endif + llvm_unreachable(); } return rv; diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 823e3162191..398a1fecc34 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -31,6 +31,8 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { @@ -600,8 +602,8 @@ static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { case ISD::SETONE: case ISD::SETOLE: case ISD::SETOGE: - assert(0 && "Should be lowered by legalize!"); - default: assert(0 && "Unknown condition!"); abort(); + LLVM_UNREACHABLE("Should be lowered by legalize!"); + default: LLVM_UNREACHABLE("Unknown condition!"); case ISD::SETOEQ: case ISD::SETEQ: return PPC::PRED_EQ; case ISD::SETUNE: @@ -632,7 +634,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { Invert = false; Other = -1; switch (CC) { - default: assert(0 && "Unknown condition!"); abort(); + default: LLVM_UNREACHABLE("Unknown condition!"); case ISD::SETOLT: case ISD::SETLT: return 0; // Bit #0 = SETOLT case ISD::SETOGT: diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 1c6b2877889..5b0c9357c0e 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -32,6 +32,8 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/DerivedTypes.h" using namespace llvm; @@ -2584,9 +2586,11 @@ SDValue PPCTargetLowering::LowerCALL_SVR4(SDValue Op, SelectionDAG &DAG, } if (Result) { +#ifndef NDEBUG cerr << "Call operand #" << i << " has unhandled type " << ArgVT.getMVTString() << "\n"; - abort(); +#endif + llvm_unreachable(); } } } else { @@ -4141,8 +4145,7 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { } return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); } else { - assert(0 && "Unknown mul to lower!"); - abort(); + LLVM_UNREACHABLE("Unknown mul to lower!"); } } diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 87c612ab74e..63adf329f4b 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -20,6 +20,8 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetAsmInfo.h" using namespace llvm; @@ -485,8 +487,7 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, .addReg(PPC::R0) .addReg(PPC::R0)); } else { - assert(0 && "Unknown regclass!"); - abort(); + LLVM_UNREACHABLE("Unknown regclass!"); } return false; @@ -537,8 +538,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } else if (RC == PPC::VRRCRegisterClass) { Opc = PPC::STVX; } else { - assert(0 && "Unknown regclass!"); - abort(); + LLVM_UNREACHABLE("Unknown regclass!"); } MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, getKillRegState(isKill)); @@ -634,8 +634,7 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) .addReg(PPC::R0)); } else { - assert(0 && "Unknown regclass!"); - abort(); + LLVM_UNREACHABLE("Unknown regclass!"); } } @@ -677,8 +676,7 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } else if (RC == PPC::VRRCRegisterClass) { Opc = PPC::LVX; } else { - assert(0 && "Unknown regclass!"); - abort(); + LLVM_UNREACHABLE("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp index 7486d749588..25f3785ad38 100644 --- a/lib/Target/PowerPC/PPCJITInfo.cpp +++ b/lib/Target/PowerPC/PPCJITInfo.cpp @@ -18,6 +18,8 @@ #include "llvm/Function.h" #include "llvm/System/Memory.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; static TargetJITInfo::JITCompilerFn JITCompilerFunction; @@ -197,8 +199,7 @@ asm( ); #else void PPC32CompilationCallback() { - assert(0 && "This is not a power pc, you can't execute this!"); - abort(); + LLVM_UNREACHABLE("This is not a power pc, you can't execute this!"); } #endif @@ -264,8 +265,7 @@ asm( ); #else void PPC64CompilationCallback() { - assert(0 && "This is not a power pc, you can't execute this!"); - abort(); + LLVM_UNREACHABLE("This is not a power pc, you can't execute this!"); } #endif diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 97b1c57d797..26d08d09832 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -37,7 +37,9 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include @@ -111,8 +113,7 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { case R30: case X30: case F30: case V30: case CR7EQ: return 30; case R31: case X31: case F31: case V31: case CR7UN: return 31; default: - cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; - abort(); + LLVM_UNREACHABLE("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); } } diff --git a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp index 9432ff0972c..04e1cc8bb61 100644 --- a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp @@ -185,7 +185,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { << MO.getIndex(); break; default: - llvm_report_error(""); break; + LLVM_UNREACHABLE(""); } if (CloseParen) O << ")"; } @@ -299,11 +299,11 @@ void SparcAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::InternalLinkage: break; case GlobalValue::GhostLinkage: - llvm_report_error("Should not have any unmaterialized functions!"); + LLVM_UNREACHABLE("Should not have any unmaterialized functions!"); case GlobalValue::DLLImportLinkage: - llvm_report_error("DLLImport linkage is not supported by this target!"); + LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - llvm_report_error("DLLExport linkage is not supported by this target!"); + LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); default: LLVM_UNREACHABLE("Unknown linkage type!"); } diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index c9bd62d0e20..e1b9b59b409 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -17,6 +17,8 @@ #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; //===----------------------------------------------------------------------===// diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp index 4f7a00a7cc0..5b10c7bdcf6 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp @@ -104,7 +104,7 @@ void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) O << DispVal; } else { - llvm_report_error("non-immediate displacement for LEA?"); + LLVM_UNREACHABLE("non-immediate displacement for LEA?"); //assert(DispSpec.isGlobal() || DispSpec.isCPI() || // DispSpec.isJTI() || DispSpec.isSymbol()); //printOperand(MI, Op+3, "mem"); diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index afb1e1dedeb..1dc6e769250 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -32,7 +32,6 @@ #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; @@ -806,10 +805,10 @@ void Emitter::emitInstruction( } if (!Desc->isVariadic() && CurOp != NumOps) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Cannot encode: " << MI; - llvm_report_error(Msg.str()); +#ifndef NDEBUG + cerr << "Cannot encode: " << MI << "\n"; +#endif + llvm_unreachable(); } } diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 1336177de24..b8cbbfa185f 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -35,8 +35,10 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Streams.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" using namespace llvm; diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 33789ce66c5..32f247df977 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -38,6 +38,7 @@ #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; static cl::opt @@ -6054,7 +6055,7 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { SDValue SrcPtr = Op.getOperand(1); SDValue SrcSV = Op.getOperand(2); - LLVM_UNREACHABLE("VAArgInst is not yet implemented for x86-64!"); + llvm_report_error("VAArgInst is not yet implemented for x86-64!"); return SDValue(); } diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp index 1b7238cb48b..6f2af779f3d 100644 --- a/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -204,13 +204,13 @@ emitGlobal(const GlobalVariable *GV) case GlobalValue::PrivateLinkage: break; case GlobalValue::GhostLinkage: - llvm_report_error("Should not have any unmaterialized functions!"); + LLVM_UNREACHABLE("Should not have any unmaterialized functions!"); case GlobalValue::DLLImportLinkage: - llvm_report_error("DLLImport linkage is not supported by this target!"); + LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - llvm_report_error("DLLExport linkage is not supported by this target!"); + LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); default: - assert(0 && "Unknown linkage type!"); + LLVM_UNREACHABLE("Unknown linkage type!"); } EmitAlignment(Align, GV, 2); diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp index eed34a4b635..5114bc75321 100644 --- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -28,6 +28,8 @@ #include "llvm/Target/TargetLowering.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include #include using namespace llvm; diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 7d0de2af2a8..c615d61de95 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -32,6 +32,7 @@ #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/VectorExtras.h" #include #include @@ -270,8 +271,11 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) } const Type *Ty = cast(GV->getType())->getElementType(); if (!Ty->isSized() || isZeroLengthArray(Ty)) { - llvm_report_error("Size of thread local object " + GVar->getName() - + " is unknown"); +#ifndef NDEBUG + cerr << "Size of thread local object " << GVar->getName() + << " is unknown\n"; +#endif + llvm_unreachable(); } SDValue base = getGlobalAddressWrapper(GA, GV, DAG); const TargetData *TD = TM.getTargetData(); @@ -646,11 +650,11 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG) switch (RegVT.getSimpleVT()) { default: { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "LowerFORMAL_ARGUMENTS Unhandled argument type: " - << RegVT.getSimpleVT(); - llvm_report_error(Msg.str()); +#ifndef NDEBUG + cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " + << RegVT.getSimpleVT() << "\n"; +#endif + llvm_unreachable(); } case MVT::i32: unsigned VReg = RegInfo.createVirtualRegister( diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index ffbace6db7f..9bf99ac0dad 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -144,11 +144,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, if (!isU6 && !isImmU16(Amount)) { // FIX could emit multiple instructions in this case. - std::string msg; - raw_string_ostream Msg(msg); - Msg << "eliminateCallFramePseudoInstr size too big: " - << Amount; - llvm_report_error(Msg.str()); +#ifndef NDEBUG + cerr << "eliminateCallFramePseudoInstr size too big: " + << Amount << "\n"; +#endif + llvm_unreachable(); } MachineInstr *New; diff --git a/lib/VMCore/AsmWriter.cpp b/lib/VMCore/AsmWriter.cpp index 70c27eb5111..ec299171982 100644 --- a/lib/VMCore/AsmWriter.cpp +++ b/lib/VMCore/AsmWriter.cpp @@ -33,6 +33,7 @@ #include "llvm/Support/CFG.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/Streams.h" #include "llvm/Support/raw_ostream.h" #include #include @@ -1235,7 +1236,7 @@ static void PrintLinkage(GlobalValue::LinkageTypes LT, raw_ostream &Out) { case GlobalValue::ExternalWeakLinkage: Out << "extern_weak "; break; case GlobalValue::ExternalLinkage: break; case GlobalValue::GhostLinkage: - llvm_report_error("GhostLinkage not allowed in AsmWriter!"); + LLVM_UNREACHABLE("GhostLinkage not allowed in AsmWriter!"); } } diff --git a/lib/VMCore/Globals.cpp b/lib/VMCore/Globals.cpp index b3087f7cc43..c3fe5683eca 100644 --- a/lib/VMCore/Globals.cpp +++ b/lib/VMCore/Globals.cpp @@ -21,6 +21,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/LeakDetector.h" +#include "llvm/Support/Streams.h" using namespace llvm; //===----------------------------------------------------------------------===// diff --git a/lib/VMCore/Instructions.cpp b/lib/VMCore/Instructions.cpp index 66269301847..bbb22c5a64b 100644 --- a/lib/VMCore/Instructions.cpp +++ b/lib/VMCore/Instructions.cpp @@ -20,6 +20,7 @@ #include "llvm/Support/CallSite.h" #include "llvm/Support/ConstantRange.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/Streams.h" using namespace llvm; //===----------------------------------------------------------------------===// diff --git a/lib/VMCore/Type.cpp b/lib/VMCore/Type.cpp index 432a1cca818..8daaf915e41 100644 --- a/lib/VMCore/Type.cpp +++ b/lib/VMCore/Type.cpp @@ -265,10 +265,10 @@ const Type *Type::getForwardedTypeInternal() const { } void Type::refineAbstractType(const DerivedType *OldTy, const Type *NewTy) { - llvm_report_error("Attempting to refine a derived type!"); + LLVM_UNREACHABLE("Attempting to refine a derived type!"); } void Type::typeBecameConcrete(const DerivedType *AbsTy) { - llvm_report_error("DerivedType is already a concrete type!"); + LLVM_UNREACHABLE("DerivedType is already a concrete type!"); } diff --git a/lib/VMCore/Value.cpp b/lib/VMCore/Value.cpp index 8c5d551c15e..0120333481c 100644 --- a/lib/VMCore/Value.cpp +++ b/lib/VMCore/Value.cpp @@ -23,6 +23,7 @@ #include "llvm/Support/LeakDetector.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/ValueHandle.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/System/RWMutex.h" #include "llvm/System/Threading.h" #include "llvm/ADT/DenseMap.h" @@ -515,8 +516,8 @@ void ValueHandleBase::ValueIsDeleted(Value *V) { cerr << "While deleting: " << *V->getType() << " %" << V->getNameStr() << "\n"; #endif - llvm_report_error("An asserting value handle still pointed to this" - "value!"); + LLVM_UNREACHABLE("An asserting value handle still pointed to this" + "value!"); case Weak: // Weak just goes to null, which will unlink it from the list. ThisNode->operator=(0); diff --git a/lib/VMCore/Verifier.cpp b/lib/VMCore/Verifier.cpp index 6674acb79de..da3fed0ff3c 100644 --- a/lib/VMCore/Verifier.cpp +++ b/lib/VMCore/Verifier.cpp @@ -211,7 +211,9 @@ namespace { default: assert(0 && "Unknown action"); case AbortProcessAction: msgs << "compilation aborted!\n"; - llvm_report_error(msgs.str()); + cerr << msgs.str(); + // Client should choose different reaction if abort is not desired + abort(); case PrintMessageAction: msgs << "verification continues.\n"; cerr << msgs.str(); -- 2.34.1