From cf5bea8e4a4bff7477617eb4b09ce36f00a5bc5e Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Thu, 18 Sep 2014 13:27:14 +0000 Subject: [PATCH] Fixing a bunch of -Woverloaded-virtual warnings due to hiding getSubtargetImpl from the base class. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218050 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64TargetMachine.h | 1 + lib/Target/ARM/ARMTargetMachine.h | 1 + lib/Target/Hexagon/HexagonTargetMachine.h | 1 + lib/Target/MSP430/MSP430TargetMachine.h | 1 + lib/Target/Mips/MipsTargetMachine.h | 1 + lib/Target/NVPTX/NVPTXTargetMachine.h | 1 + lib/Target/PowerPC/PPCTargetMachine.h | 1 + lib/Target/R600/AMDGPUTargetMachine.h | 2 ++ lib/Target/Sparc/SparcTargetMachine.h | 1 + lib/Target/SystemZ/SystemZTargetMachine.h | 1 + lib/Target/X86/X86TargetMachine.h | 2 ++ lib/Target/XCore/XCoreTargetMachine.h | 1 + 12 files changed, 14 insertions(+) diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h index 42d7dc57328..af692de7430 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.h +++ b/lib/Target/AArch64/AArch64TargetMachine.h @@ -31,6 +31,7 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool IsLittleEndian); + using LLVMTargetMachine::getSubtargetImpl; const AArch64Subtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index 3a7887f5edf..dfbf45d12fd 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -32,6 +32,7 @@ public: CodeGenOpt::Level OL, bool isLittle); + using LLVMTargetMachine::getSubtargetImpl; const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; } /// \brief Register ARM analysis passes with a pass manager. diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h index d917d5b89a1..d2bba73c34e 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/lib/Target/Hexagon/HexagonTargetMachine.h @@ -31,6 +31,7 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + using LLVMTargetMachine::getSubtargetImpl; const HexagonSubtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/MSP430/MSP430TargetMachine.h b/lib/Target/MSP430/MSP430TargetMachine.h index 5c73c831f5e..597629d3e81 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.h +++ b/lib/Target/MSP430/MSP430TargetMachine.h @@ -32,6 +32,7 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + using LLVMTargetMachine::getSubtargetImpl; const MSP430Subtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index 58400cd1b48..43b62562346 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -39,6 +39,7 @@ public: void addAnalysisPasses(PassManagerBase &PM) override; + using LLVMTargetMachine::getSubtargetImpl; const MipsSubtarget *getSubtargetImpl() const override { if (Subtarget) return Subtarget; diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.h b/lib/Target/NVPTX/NVPTXTargetMachine.h index 3dca4da724a..7cc03cb7de8 100644 --- a/lib/Target/NVPTX/NVPTXTargetMachine.h +++ b/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -35,6 +35,7 @@ public: const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit); + using LLVMTargetMachine::getSubtargetImpl; const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; } ManagedStringPool *getManagedStrPool() const { diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index ea7f27ae18a..c503ec2fdc7 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -32,6 +32,7 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + using LLVMTargetMachine::getSubtargetImpl; const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; } // Pass Pipeline Configuration diff --git a/lib/Target/R600/AMDGPUTargetMachine.h b/lib/Target/R600/AMDGPUTargetMachine.h index ff581b5c9aa..14411e97bb9 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.h +++ b/lib/Target/R600/AMDGPUTargetMachine.h @@ -33,6 +33,8 @@ public: StringRef CPU, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); ~AMDGPUTargetMachine(); + + using LLVMTargetMachine::getSubtargetImpl; const AMDGPUSubtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index 142929ca60e..4b071ba9378 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -28,6 +28,7 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit); + using LLVMTargetMachine::getSubtargetImpl; const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; } // Pass Pipeline Configuration diff --git a/lib/Target/SystemZ/SystemZTargetMachine.h b/lib/Target/SystemZ/SystemZTargetMachine.h index c5f982395a1..45ff61f6b78 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/lib/Target/SystemZ/SystemZTargetMachine.h @@ -32,6 +32,7 @@ public: CodeGenOpt::Level OL); // Override TargetMachine. + using LLVMTargetMachine::getSubtargetImpl; const SystemZSubtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 8783bab5d95..b7042e1f0a7 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -31,6 +31,8 @@ public: StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + + using LLVMTargetMachine::getSubtargetImpl; const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; } /// \brief Register X86 analysis passes with a pass manager. diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index 32360996bba..e6654f3b062 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -27,6 +27,7 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + using LLVMTargetMachine::getSubtargetImpl; const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; } // Pass Pipeline Configuration -- 2.34.1