From cf20e45cc4cb77bcb16363531e600883cd27ff80 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 25 Jul 2013 09:04:52 +0000 Subject: [PATCH] [SystemZ] Add LOC and LOCG As with the stores, these instructions can trap when the condition is false, so they are only used for things like (cond ? x : *ptr). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187112 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZInstrFormats.td | 40 +++++++ lib/Target/SystemZ/SystemZInstrInfo.td | 14 +++ lib/Target/SystemZ/SystemZOperands.td | 9 ++ lib/Target/SystemZ/SystemZPatterns.td | 12 ++ test/CodeGen/SystemZ/cond-load-01.ll | 130 ++++++++++++++++++++++ test/CodeGen/SystemZ/cond-load-02.ll | 130 ++++++++++++++++++++++ test/MC/Disassembler/SystemZ/insns.txt | 96 ++++++++++++++++ test/MC/SystemZ/insn-bad-z196.s | 34 ++++++ test/MC/SystemZ/insn-good-z196.s | 96 ++++++++++++++++ 9 files changed, 561 insertions(+) create mode 100644 test/CodeGen/SystemZ/cond-load-01.ll create mode 100644 test/CodeGen/SystemZ/cond-load-02.ll diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index b92c350fdd8..8199c176d79 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -704,6 +704,46 @@ class UnaryRILPC opcode, SDPatternOperator operator, let AddedComplexity = 7; } +class CondUnaryRSY opcode, + RegisterOperand cls, bits<5> bytes, + AddressingMode mode = bdaddr20only> + : InstRSY, + Requires<[FeatureLoadStoreOnCond]> { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; + let mayLoad = 1; + let AccessBytes = bytes; +} + +// Like CondUnaryRSY, but used for the raw assembly form. The condition-code +// mask is the third operand rather than being part of the mnemonic. +class AsmCondUnaryRSY opcode, + RegisterOperand cls, bits<5> bytes, + AddressingMode mode = bdaddr20only> + : InstRSY, + Requires<[FeatureLoadStoreOnCond]> { + let mayLoad = 1; + let AccessBytes = bytes; + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; +} + +// Like CondUnaryRSY, but with a fixed CC mask. +class FixedCondUnaryRSY opcode, + RegisterOperand cls, bits<4> ccmask, bits<5> bytes, + AddressingMode mode = bdaddr20only> + : InstRSY, + Requires<[FeatureLoadStoreOnCond]> { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; + let R3 = ccmask; + let mayLoad = 1; + let AccessBytes = bytes; +} + class UnaryRX opcode, SDPatternOperator operator, RegisterOperand cls, bits<5> bytes, AddressingMode mode = bdxaddr12only> diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index bda34dfb599..46cd7644786 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -112,6 +112,8 @@ multiclass CondExtendedMnemonic ccmask, string name> { def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg"##name##"\t$I2", []>; } + def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>; + def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>; def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>; def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>; } @@ -259,6 +261,18 @@ let canFoldAsLoad = 1 in { def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; } +// Load on condition. +let isCodeGenOnly = 1, Uses = [CC] in { + def LOC : CondUnaryRSY<"loc", 0xEBF2, GR32, 4>; + def LOCG : CondUnaryRSY<"locg", 0xEBE2, GR64, 8>; +} +let Uses = [CC] in { + def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>; + def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>; +} +defm : CondLoad; +defm : CondLoad; + // Register stores. let SimpleBDXStore = 1 in { let isCodeGenOnly = 1 in diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td index 9d794392280..696ec4f15a1 100644 --- a/lib/Target/SystemZ/SystemZOperands.td +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -110,6 +110,15 @@ class BDLMode("disp"##dispsize##"imm"##bitsize), !cast("imm"##bitsize))>; +//===----------------------------------------------------------------------===// +// Manipulating CC masks +//===----------------------------------------------------------------------===// + +def INVCC : SDNodeXFormgetZExtValue() ^ SystemZ::CCMASK_ANY; + return CurDAG->getTargetConstant(Value, MVT::i8); +}]>; + //===----------------------------------------------------------------------===// // Extracting immediate operands from nodes // These all create MVT::i64 nodes to ensure the value is not sign-extended diff --git a/lib/Target/SystemZ/SystemZPatterns.td b/lib/Target/SystemZ/SystemZPatterns.td index 74cc5f019a8..4e4386a3984 100644 --- a/lib/Target/SystemZ/SystemZPatterns.td +++ b/lib/Target/SystemZ/SystemZPatterns.td @@ -54,6 +54,18 @@ multiclass RMWIByte; } +// Record that INSN conditionally performs load operation LOAD into a +// register of class CLS. The load may trap even if the condition is false. +multiclass CondLoad { + def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4:$cc), + (insn cls:$new, bdaddr20only:$addr, uimm8zx4:$cc)>, + Requires<[FeatureLoadStoreOnCond]>; + def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4:$cc), + (insn cls:$new, bdaddr20only:$addr, (INVCC uimm8zx4:$cc))>, + Requires<[FeatureLoadStoreOnCond]>; +} + // Record that INSN performs insertion TYPE into a register of class CLS. // The inserted operand is loaded using LOAD from an address of mode MODE. multiclass InsertMem