From be6781b5d00107f4b60797c3ebdc0aab110487ff Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 6 Nov 2007 21:12:10 +0000 Subject: [PATCH] When the allocator rewrite a spill register with new virtual register, it replaces other operands of the same register. Watch out for situations where only some of the operands are sub-register uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43776 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/LiveIntervalAnalysis.cpp | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 9301c28015c..929b1e7e92d 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -379,10 +379,19 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, unsigned reg) { if (!MI->getOperand(j).isRegister()) continue; unsigned RegJ = MI->getOperand(j).getReg(); - if (RegJ != 0 && MRegisterInfo::isVirtualRegister(RegJ) && - RegMap->isSubRegister(RegJ)) + if (RegJ == 0 || MRegisterInfo::isPhysicalRegister(RegJ)) + continue; + bool isSubRegJ = RegMap->isSubRegister(RegJ); + if (isSubRegJ) { + assert(!isSubReg || RegMap->getSubRegisterIndex(RegJ) == SubIdx); RegJ = RegMap->getSuperRegister(RegJ); - if (RegJ == li.reg) { + } + // Important to check "isSubRegJ == isSubReg". + // e.g. %reg1024 = MOVSX32rr16 %reg1025. It's possible that both + // registers are coalesced to the same register but only %reg1025 is + // a sub-register use. They should not be rewritten to the same + // register. + if (RegJ == li.reg && isSubRegJ == isSubReg) { MI->getOperand(j).setReg(NewVReg); HasUse |= MI->getOperand(j).isUse(); HasDef |= MI->getOperand(j).isDef(); -- 2.34.1