From bd80605e28cc4103e87d628ffc7d5293893bee06 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Thu, 15 May 2014 14:54:06 +0000 Subject: [PATCH] [mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructions Differential Revision: http://reviews.llvm.org/D3709 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208890 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips32r6InstrInfo.td | 42 +++++++++++++++++++++++----- test/MC/Mips/mips32r6/valid.s | 8 ++++++ test/MC/Mips/mips64r6/valid.s | 8 ++++++ 3 files changed, 51 insertions(+), 7 deletions(-) diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 68135c5c1c9..78088bdd764 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -75,6 +75,16 @@ class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>; class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>; class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>; +class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>; +class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>; +class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>; +class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>; + +class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>; +class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>; +class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>; +class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>; + //===----------------------------------------------------------------------===// // // Instruction Descriptions @@ -163,6 +173,23 @@ class SEL_DESC_BASE { class SEL_D_DESC : SEL_DESC_BASE<"sel.d", FGR64Opnd>; class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>; +class MAX_MIN_DESC_BASE { + dag OutOperandList = (outs FGROpnd:$fd); + dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); + string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); + list Pattern = []; +} + +class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>; +class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>; +class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>; +class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>; + +class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>; +class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>; +class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>; +class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -213,13 +240,14 @@ def JIC; def LWPC; def LWUPC; def MADDF; -def MAXA_D; -def MAXA_S; -def MAX_D; -def MAX_S; -def MINA_D; -def MINA_S; -def MIN_D; +def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6; +def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6; +def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6; +def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6; +def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6; +def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6; +def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6; +def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6; def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6; def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6; def MSUBF; diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index 1ae5c6bb021..9de69c1d014 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -20,3 +20,11 @@ muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] + max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] + max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] + min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c] + min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c] + maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f] + maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] + mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] + mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index 257c9e5728f..86864b330cf 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -33,3 +33,11 @@ dmuhu $2,$3,$4 # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf9] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] + max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] + max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] + min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c] + min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c] + maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f] + maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] + mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] + mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] -- 2.34.1