From ba4a99ac26579b1dc9e88b059138a8ed6e7bd929 Mon Sep 17 00:00:00 2001 From: Zlatko Buljan Date: Mon, 21 Dec 2015 13:08:58 +0000 Subject: [PATCH] [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256152 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 6 +++ .../Mips/Disassembler/MipsDisassembler.cpp | 14 ------ .../Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 9 ---- .../Mips/MCTargetDesc/MipsMCCodeEmitter.h | 3 -- lib/Target/Mips/MicroMips32r6InstrFormats.td | 8 ++-- lib/Target/Mips/MicroMips32r6InstrInfo.td | 13 ++++-- lib/Target/Mips/MicroMips64r6InstrInfo.td | 16 ++++--- lib/Target/Mips/MicroMipsInstrInfo.td | 7 +-- lib/Target/Mips/Mips64InstrInfo.td | 12 +++-- lib/Target/Mips/MipsInstrInfo.td | 46 ++++++++++++------- .../Disassembler/Mips/micromips32r6/valid.txt | 3 ++ .../Disassembler/Mips/micromips64r6/valid.txt | 3 ++ test/MC/Mips/micromips/invalid.s | 3 ++ test/MC/Mips/micromips32r6/invalid.s | 3 ++ test/MC/Mips/micromips32r6/valid.s | 4 ++ test/MC/Mips/micromips64r6/invalid.s | 17 +++++-- test/MC/Mips/micromips64r6/valid.s | 6 ++- test/MC/Mips/mips32r2/invalid.s | 4 +- test/MC/Mips/mips64r2/invalid.s | 18 ++++++-- 19 files changed, 126 insertions(+), 69 deletions(-) diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 4e7a20130ae..d4e061f00d3 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3636,9 +3636,15 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_UImm5_0: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 5-bit unsigned immediate"); + case Match_UImm5_1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range 1 .. 32"); case Match_UImm5_32: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 32 .. 63"); + case Match_UImm5_33: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range 33 .. 64"); case Match_UImm5_0_Report_UImm6: // This is used on UImm5 operands that have a corresponding UImm5_32 // operand to avoid confusing the user. diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 716a96e2c46..3c1a771f97e 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -396,11 +396,6 @@ static DecodeStatus DecodeInsSize(MCInst &Inst, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeExtSize(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); - static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); @@ -1965,15 +1960,6 @@ static DecodeStatus DecodeInsSize(MCInst &Inst, return MCDisassembler::Success; } -static DecodeStatus DecodeExtSize(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { - int Size = (int) Insn + 1; - Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); - return MCDisassembler::Success; -} - static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index ed917a4daba..4b030ebfce8 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -865,15 +865,6 @@ getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, return ((OffBits >> 2) & 0x0F); } -unsigned -MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const { - assert(MI.getOperand(OpNo).isImm()); - unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); - return SizeEncoding - 1; -} - // FIXME: should be called getMSBEncoding // unsigned diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h index eb48914b064..fdacd172e3a 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -191,9 +191,6 @@ public: unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; - unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const; unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; diff --git a/lib/Target/Mips/MicroMips32r6InstrFormats.td b/lib/Target/Mips/MicroMips32r6InstrFormats.td index 349b3b88a07..400f6eef3fb 100644 --- a/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -473,12 +473,13 @@ class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6 funct> : MipsR6Inst { let Inst{15-0} = offset; } -class ERET_FM_MMR6 : MMR6Arch { +class POOL32A_ERET_FM_MMR6 funct> + : MMR6Arch { bits<32> Inst; let Inst{31-26} = 0x00; let Inst{25-16} = 0x00; - let Inst{15-6} = 0x3cd; + let Inst{15-6} = funct; let Inst{5-0} = 0x3c; } @@ -513,7 +514,8 @@ class BARRIER_MMR6_ENC op> : MMR6Arch { let Inst{5-0} = 0x0; } -class EIDI_MMR6_ENC funct> : MMR6Arch { +class POOL32A_EIDI_MMR6_ENC funct> + : MMR6Arch { bits<32> Inst; bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index 8c744d8924b..31b5db036da 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -52,8 +52,10 @@ class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>; class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>; class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>; class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>; -class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>; -class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">; +class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>; +class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>; +class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>; +class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>; class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">; class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>; class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>; @@ -361,8 +363,10 @@ class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>; class EHB_MMR6_DESC : Barrier<"ehb">; class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>; +class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd>; class ERET_MMR6_DESC : ER_FT<"eret">; +class DERET_MMR6_DESC : ER_FT<"deret">; class ERETNC_MMR6_DESC : ER_FT<"eretnc">; class JALRC16_MMR6_DESC_BASE @@ -968,7 +972,9 @@ def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6; def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6; def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6; def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6; -def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6; +def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6; +def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6; +def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6; def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC, ISA_MICROMIPS32R6; def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC, @@ -1205,6 +1211,7 @@ def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC, //===----------------------------------------------------------------------===// def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6; +def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6; def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6; def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset), !strconcat("b", "\t$offset")> { diff --git a/lib/Target/Mips/MicroMips64r6InstrInfo.td b/lib/Target/Mips/MicroMips64r6InstrInfo.td index f9e6a3c2f6c..ec1aef86a94 100644 --- a/lib/Target/Mips/MicroMips64r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -55,21 +55,25 @@ class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>; class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>; class EXTBITS_DESC_BASE : MMR6Arch, MipsR6Inst { + Operand SizeOpnd, SDPatternOperator Op = null_frag> + : MMR6Arch, MipsR6Inst { dag OutOperandList = (outs RO:$rt); - dag InOperandList = (ins RO:$rs, PosOpnd:$pos, size_ext:$size); + dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size"); list Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))]; InstrItinClass Itinerary = II_EXT; Format Form = FrmR; string BaseOpcode = instr_asm; } -class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm6, - MipsExt>; +// TODO: Add 'pos + size' constraint check to dext* instructions +// DEXT: 0 < pos + size <= 63 +// DEXTM, DEXTU: 32 < pos + size <= 64 +class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5, + uimm5_plus1, MipsExt>; class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5, - MipsExt>; + uimm5_plus33, MipsExt>; class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32, - MipsExt>; + uimm5_plus1, MipsExt>; class DALIGN_DESC_BASE : MMR6Arch, MipsR6Inst { diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 175a9559e00..99f0f446dea 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -844,9 +844,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Word Swap Bytes Within Halfwords def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM_MM<0x1ec>, ISA_MIPS32R2; - - def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, - EXT_FM_MM<0x2c>; + // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction + def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, + MipsExt>, EXT_FM_MM<0x2c>; def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM_MM<0x0c>; @@ -1018,6 +1018,7 @@ def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS; let Predicates = [InMicroMips] in { def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2; +def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"teq $rs, $rt", (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tge $rs, $rt", diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index b0cf96dbd75..cbdcdd788be 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -273,9 +273,15 @@ let isCodeGenOnly = 1 in def RDHWR64 : ReadHardware, RDHWR_FM; let AdditionalPredicates = [NotInMicroMips] in { - def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>; - def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>; - def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32>, EXT_FM<2>; + // TODO: Add 'pos + size' constraint check to dext* instructions + // DEXT: 0 < pos + size <= 63 + // DEXTM, DEXTU: 32 < pos + size <= 64 + def DEXT : ExtBase<"dext", GPR64Opnd, uimm5, uimm5_plus1, MipsExt>, + EXT_FM<3>; + def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, MipsExt>, + EXT_FM<1>; + def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, + MipsExt>, EXT_FM<2>; } def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 6d83cceab40..d9fb8c89073 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -413,8 +413,12 @@ def ConstantUImm6AsmOperandClass : ConstantUImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>; def ConstantSImm6AsmOperandClass : ConstantSImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>; +def ConstantUImm5Plus1AsmOperandClass + : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 1>; def ConstantUImm5Plus32AsmOperandClass : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32>; +def ConstantUImm5Plus33AsmOperandClass + : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 33>; def ConstantUImm5Plus32NormalizeAsmOperandClass : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32> { let Name = "ConstantUImm5_32_Norm"; @@ -536,11 +540,25 @@ def uimm2_plus1 : Operand { let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass; } +def uimm5_plus1 : Operand { + let PrintMethod = "printUnsignedImm"; + let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; + let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; + let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass; +} + def uimm5_plus32 : Operand { let PrintMethod = "printUnsignedImm"; let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass; } +def uimm5_plus33 : Operand { + let PrintMethod = "printUnsignedImm"; + let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; + let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; + let ParserMatchClass = ConstantUImm5Plus33AsmOperandClass; +} + def uimm5_plus32_normalize : Operand { let PrintMethod = "printUnsignedImm"; let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; @@ -683,12 +701,6 @@ def PtrRC : Operand { let ParserMatchClass = GPR32AsmOperand; } -// size operand of ext instruction -def size_ext : Operand { - let EncoderMethod = "getSizeExtEncoding"; - let DecoderMethod = "DecodeExtSize"; -} - // size operand of ins instruction def size_ins : Operand { let EncoderMethod = "getSizeInsEncoding"; @@ -1187,8 +1199,8 @@ class ReadHardware : // Ext and Ins class ExtBase: - InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size), + Operand SizeOpnd, SDPatternOperator Op = null_frag> : + InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size), !strconcat(opstr, " $rt, $rs, $pos, $size"), [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT, FrmR, opstr>, ISA_MIPS32R2; @@ -1473,15 +1485,15 @@ def TRAP : TrapBase; def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; let AdditionalPredicates = [NotInMicroMips] in { -def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32; -def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5; + def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32; + def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5; + def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32; } -def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32; let AdditionalPredicates = [NotInMicroMips] in { -def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; + def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; + def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2; } -def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2; let EncodingPredicates = [], // FIXME: Lack of HasStdEnc is probably a bug AdditionalPredicates = [NotInMicroMips] in { @@ -1676,7 +1688,9 @@ def PseudoUDIV : MultDivPseudo, RDHWR_FM; } -def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; +// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction +def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, MipsExt>, + EXT_FM<0>; def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; /// Move Control Registers From/To CPU Registers @@ -1871,9 +1885,9 @@ def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; def : MipsInstAlias<"break", (BREAK 0, 0), 1>; def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; let AdditionalPredicates = [NotInMicroMips] in { -def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; + def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; + def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; } -def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; diff --git a/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/test/MC/Disassembler/Mips/micromips32r6/valid.txt index 5fa2138262a..b8e69f833a0 100644 --- a/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -53,6 +53,7 @@ 0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5) 0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp +0x00 0x00 0xe3 0x7c # CHECK: deret 0x00 0xa4 0x19 0x18 # CHECK: div $3, $4, $5 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5 0x00 0x00 0x18 0x00 # CHECK: ehb @@ -253,3 +254,5 @@ 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 +0x00 0x00 0x47 0x7c # CHECK: di +0x00 0x0f 0x47 0x7c # CHECK: di $15 diff --git a/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/test/MC/Disassembler/Mips/micromips64r6/valid.txt index 10a9687384e..4f2325fe7ce 100644 --- a/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -166,3 +166,6 @@ 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 +0x00 0x00 0xe3 0x7c # CHECK: deret +0x00 0x00 0x47 0x7c # CHECK: di +0x00 0x0f 0x47 0x7c # CHECK: di $15 diff --git a/test/MC/Mips/micromips/invalid.s b/test/MC/Mips/micromips/invalid.s index 2bb7886eb2a..b091062fdcc 100644 --- a/test/MC/Mips/micromips/invalid.s +++ b/test/MC/Mips/micromips/invalid.s @@ -11,8 +11,11 @@ break16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + # FIXME: Check '0 < pos + size <= 32' constraint on ext ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 + ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate jraddiusp -1 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4 diff --git a/test/MC/Mips/micromips32r6/invalid.s b/test/MC/Mips/micromips32r6/invalid.s index 92d3f70c65a..41c661b0492 100644 --- a/test/MC/Mips/micromips32r6/invalid.s +++ b/test/MC/Mips/micromips32r6/invalid.s @@ -25,8 +25,11 @@ break 1023, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + # FIXME: Check '0 < pos + size <= 32' constraint on ext ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 + ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index 194b15e1a4f..62048a91163 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -45,6 +45,9 @@ ei # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c] ei $0 # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c] ei $10 # CHECK: ei $10 # encoding: [0x00,0x0a,0x57,0x7c] + di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] + di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] + di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c] eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c] eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c] jalr $9 # CHECK: jalr $9 # encoding: [0x45,0x2b] @@ -246,3 +249,4 @@ selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78] class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] + deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] diff --git a/test/MC/Mips/micromips64r6/invalid.s b/test/MC/Mips/micromips64r6/invalid.s index 67d7d8b2350..df1005dfa0b 100644 --- a/test/MC/Mips/micromips64r6/invalid.s +++ b/test/MC/Mips/micromips64r6/invalid.s @@ -18,13 +18,21 @@ bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate - # FIXME: Check size on dext* - dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate - dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate + # FIXME: Check various 'pos + size' constraints on dext* + dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate + dext $2, $3, 32, 1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate + dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32 + dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32 dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate dextm $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate + dextm $2, $3, -1, 33 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate + dextm $2, $3, 32, 33 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate + dextm $2, $3, 1, 32 # CHECK: :[[@LINE]]:20: error: expected immediate in range 33 .. 64 + dextm $2, $3, 1, 65 # CHECK: :[[@LINE]]:20: error: expected immediate in range 33 .. 64 dextu $2, $3, 31, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63 dextu $2, $3, 64, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63 + dextu $2, $3, 32, 0 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32 + dextu $2, $3, 32, 33 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32 # FIXME: Check size on dins* dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate dins $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate @@ -32,8 +40,11 @@ dinsm $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate dinsu $2, $3, 31, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63 dinsu $2, $3, 64, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63 + # FIXME: Check '0 < pos + size <= 32' constraint on ext ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 + ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate dalign $4, $2, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate diff --git a/test/MC/Mips/micromips64r6/valid.s b/test/MC/Mips/micromips64r6/valid.s index 441d9693ad6..b41c86bd553 100644 --- a/test/MC/Mips/micromips64r6/valid.s +++ b/test/MC/Mips/micromips64r6/valid.s @@ -18,7 +18,7 @@ a: dahi $3, 4 # CHECK: dahi $3, 4 # encoding: [0x42,0x23,0x00,0x04] dati $3, 4 # CHECK: dati $3, 4 # encoding: [0x42,0x03,0x00,0x04] dext $9, $6, 3, 7 # CHECK: dext $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xec] - dextm $9, $6, 3, 7 # CHECK: dextm $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xe4] + dextm $9, $6, 3, 39 # CHECK: dextm $9, $6, 3, 39 # encoding: [0x59,0x26,0x30,0xe4] dextu $9, $6, 35, 7 # CHECK: dextu $9, $6, 35, 7 # encoding: [0x59,0x26,0x30,0xd4] dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c] lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88] @@ -146,5 +146,9 @@ a: selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78] class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] + deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] + di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] + di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] + di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c] 1: diff --git a/test/MC/Mips/mips32r2/invalid.s b/test/MC/Mips/mips32r2/invalid.s index 7d4349c2f68..6001aeacf9b 100644 --- a/test/MC/Mips/mips32r2/invalid.s +++ b/test/MC/Mips/mips32r2/invalid.s @@ -8,9 +8,11 @@ .set noreorder cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate - # FIXME: Check size on ext + # FIXME: Check '0 < pos + size <= 32' constraint on ext ext $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate ext $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate + ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:24: error: expected immediate in range 1 .. 32 + ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:24: error: expected immediate in range 1 .. 32 # FIXME: Check size on ins ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/mips64r2/invalid.s b/test/MC/Mips/mips64r2/invalid.s index edb2d898c1c..86bfc959fff 100644 --- a/test/MC/Mips/mips64r2/invalid.s +++ b/test/MC/Mips/mips64r2/invalid.s @@ -8,13 +8,21 @@ .set noreorder cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate - # FIXME: Check size on dext* - dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate - dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate + # FIXME: Check various 'pos + size' constraints on dext* + dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate + dext $2, $3, 32, 1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate + dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32 + dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32 dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate dextm $2, $3, 32, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate + dextm $2, $3, -1, 33 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate + dextm $2, $3, 32, 33 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate + dextm $2, $3, 1, 32 # CHECK: :[[@LINE]]:26: error: expected immediate in range 33 .. 64 + dextm $2, $3, 1, 65 # CHECK: :[[@LINE]]:26: error: expected immediate in range 33 .. 64 dextu $2, $3, 31, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63 dextu $2, $3, 64, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63 + dextu $2, $3, 32, 0 # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32 + dextu $2, $3, 32, 33 # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32 # FIXME: Check size on dins* dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate dins $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate @@ -38,9 +46,11 @@ dsra $2, $3, 64 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate dsra32 $2, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate dsra32 $2, $3, 64 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate - # FIXME: Check size on ext + # FIXME: Check '0 < pos + size <= 32' constraint on ext ext $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate ext $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate + ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:24: error: expected immediate in range 1 .. 32 + ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:24: error: expected immediate in range 1 .. 32 # FIXME: Check size on ins ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate -- 2.34.1