From ba08e46435ba84e0eefae88d2a209b041f97a691 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Wed, 23 Jul 2014 22:27:10 +0000 Subject: [PATCH] Reorganize and simplify local variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213809 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../SelectionDAG/ResourcePriorityQueue.cpp | 24 +++++++++---------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp b/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp index 624003f5070..8380a6f5bca 100644 --- a/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp +++ b/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp @@ -40,19 +40,17 @@ static cl::opt RegPressureThreshold( "dfa-sched-reg-pressure-threshold", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Track reg pressure and switch priority to in-depth")); - -ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS) : - Picker(this), - InstrItins(IS->getTargetLowering()->getTargetMachine().getInstrItineraryData()) -{ - TII = IS->getTargetLowering()->getTargetMachine().getInstrInfo(); - TRI = IS->getTargetLowering()->getTargetMachine().getRegisterInfo(); - TLI = IS->getTargetLowering(); - - const TargetMachine &tm = (*IS->MF).getTarget(); - ResourcesModel = tm.getInstrInfo()->CreateTargetScheduleState(&tm,nullptr); - // This hard requirement could be relaxed, but for now - // do not let it procede. +ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS) + : Picker(this), + InstrItins( + IS->getTargetLowering()->getTargetMachine().getInstrItineraryData()) { + const TargetMachine &TM = (*IS->MF).getTarget(); + TRI = TM.getRegisterInfo(); + TLI = IS->getTargetLowering(); + TII = TM.getInstrInfo(); + ResourcesModel = TII->CreateTargetScheduleState(&TM, nullptr); + // This hard requirement could be relaxed, but for now + // do not let it procede. assert (ResourcesModel && "Unimplemented CreateTargetScheduleState."); unsigned NumRC = TRI->getNumRegClasses(); -- 2.34.1