From b84f890bc31460a416805272ca4799db9ed4b6b1 Mon Sep 17 00:00:00 2001 From: Joerg Sonnenberger Date: Tue, 6 May 2014 20:43:01 +0000 Subject: [PATCH] If a function needs a frame pointer, but r11 (aka fp) has not been used, remove it from the list of unspilled registers. Otherwise the following attempt to keep the stack aligned by picking an extra GPR register to spill will not work as it picks up r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208129 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMFrameLowering.cpp | 4 +++ test/CodeGen/ARM/debug-frame-vararg.ll | 9 ++--- test/CodeGen/ARM/debug-frame.ll | 11 +++--- test/CodeGen/ARM/ehabi.ll | 12 +++---- test/CodeGen/ARM/interrupt-attr.ll | 38 ++++++++++---------- test/CodeGen/ARM/segmented-stacks-dynamic.ll | 4 +-- 6 files changed, 42 insertions(+), 36 deletions(-) diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp index c9000156960..5a114a94e6f 100644 --- a/lib/Target/ARM/ARMFrameLowering.cpp +++ b/lib/Target/ARM/ARMFrameLowering.cpp @@ -1529,6 +1529,10 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, if (hasFP(MF)) { MRI.setPhysRegUsed(FramePtr); + auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(), + FramePtr); + if (FPPos != UnspilledCS1GPRs.end()) + UnspilledCS1GPRs.erase(FPPos); NumGPRSpills++; } diff --git a/test/CodeGen/ARM/debug-frame-vararg.ll b/test/CodeGen/ARM/debug-frame-vararg.ll index 9b39525e527..42ff82d8153 100644 --- a/test/CodeGen/ARM/debug-frame-vararg.ll +++ b/test/CodeGen/ARM/debug-frame-vararg.ll @@ -75,12 +75,13 @@ ; CHECK-FP-ELIM: .cfi_startproc ; CHECK-FP-ELIM: sub sp, sp, #16 ; CHECK-FP-ELIM: .cfi_def_cfa_offset 16 -; CHECK-FP-ELIM: push {r4, r11, lr} -; CHECK-FP-ELIM: .cfi_def_cfa_offset 28 +; CHECK-FP-ELIM: push {r4, r10, r11, lr} +; CHECK-FP-ELIM: .cfi_def_cfa_offset 32 ; CHECK-FP-ELIM: .cfi_offset lr, -20 ; CHECK-FP-ELIM: .cfi_offset r11, -24 -; CHECK-FP-ELIM: .cfi_offset r4, -28 -; CHECK-FP-ELIM: add r11, sp, #4 +; CHECK-FP-ELIM: .cfi_offset r10, -28 +; CHECK-FP-ELIM: .cfi_offset r4, -32 +; CHECK-FP-ELIM: add r11, sp, #8 ; CHECK-FP-ELIM: .cfi_def_cfa r11, 24 ; CHECK-THUMB-FP-LABEL: sum diff --git a/test/CodeGen/ARM/debug-frame.ll b/test/CodeGen/ARM/debug-frame.ll index cf687676fb1..cb54aa8aec7 100644 --- a/test/CodeGen/ARM/debug-frame.ll +++ b/test/CodeGen/ARM/debug-frame.ll @@ -201,12 +201,13 @@ declare void @_ZSt9terminatev() ; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd: ; CHECK-V7-FP: .cfi_startproc -; CHECK-V7-FP: push {r4, r11, lr} -; CHECK-V7-FP: .cfi_def_cfa_offset 12 +; CHECK-V7-FP: push {r4, r10, r11, lr} +; CHECK-V7-FP: .cfi_def_cfa_offset 16 ; CHECK-V7-FP: .cfi_offset lr, -4 ; CHECK-V7-FP: .cfi_offset r11, -8 -; CHECK-V7-FP: .cfi_offset r4, -12 -; CHECK-V7-FP: add r11, sp, #4 +; CHECK-V7-FP: .cfi_offset r10, -12 +; CHECK-V7-FP: .cfi_offset r4, -16 +; CHECK-V7-FP: add r11, sp, #8 ; CHECK-V7-FP: .cfi_def_cfa r11, 8 ; CHECK-V7-FP: vpush {d8, d9, d10, d11, d12} ; CHECK-V7-FP: .cfi_offset d12, -24 @@ -214,7 +215,7 @@ declare void @_ZSt9terminatev() ; CHECK-V7-FP: .cfi_offset d10, -40 ; CHECK-V7-FP: .cfi_offset d9, -48 ; CHECK-V7-FP: .cfi_offset d8, -56 -; CHECK-V7-FP: sub sp, sp, #28 +; CHECK-V7-FP: sub sp, sp, #24 ; CHECK-V7-FP: .cfi_endproc ; CHECK-V7-FP-ELIM-LABEL: _Z4testiiiiiddddd: diff --git a/test/CodeGen/ARM/ehabi.ll b/test/CodeGen/ARM/ehabi.ll index 720cc3ce870..8723b4b55c7 100644 --- a/test/CodeGen/ARM/ehabi.ll +++ b/test/CodeGen/ARM/ehabi.ll @@ -148,14 +148,14 @@ declare void @_ZSt9terminatev() ; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd: ; CHECK-V7-FP: .fnstart -; CHECK-V7-FP: .save {r4, r11, lr} -; CHECK-V7-FP: push {r4, r11, lr} -; CHECK-V7-FP: .setfp r11, sp, #4 -; CHECK-V7-FP: add r11, sp, #4 +; CHECK-V7-FP: .save {r4, r10, r11, lr} +; CHECK-V7-FP: push {r4, r10, r11, lr} +; CHECK-V7-FP: .setfp r11, sp, #8 +; CHECK-V7-FP: add r11, sp, #8 ; CHECK-V7-FP: .vsave {d8, d9, d10, d11, d12} ; CHECK-V7-FP: vpush {d8, d9, d10, d11, d12} -; CHECK-V7-FP: .pad #28 -; CHECK-V7-FP: sub sp, sp, #28 +; CHECK-V7-FP: .pad #24 +; CHECK-V7-FP: sub sp, sp, #24 ; CHECK-V7-FP: .personality __gxx_personality_v0 ; CHECK-V7-FP: .handlerdata ; CHECK-V7-FP: .fnend diff --git a/test/CodeGen/ARM/interrupt-attr.ll b/test/CodeGen/ARM/interrupt-attr.ll index 9b7b41ba7ec..c5be6674da1 100644 --- a/test/CodeGen/ARM/interrupt-attr.ll +++ b/test/CodeGen/ARM/interrupt-attr.ll @@ -12,13 +12,13 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; Also need special function return setting pc and CPSR simultaneously. ; CHECK-A-LABEL: irq_fn: -; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr} -; CHECK-A: add r11, sp, #16 -; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} +; CHECK-A: add r11, sp, #20 +; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; CHECK-A: bl bar -; CHECK-A: sub sp, r11, #16 -; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr} +; CHECK-A: sub sp, r11, #20 +; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: subs pc, lr, #4 ; CHECK-A-THUMB-LABEL: irq_fn: @@ -35,15 +35,15 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to ; appropriate sentinel so no special return needed). ; CHECK-M-LABEL: irq_fn: -; CHECK-M: push {r4, r7, lr} -; CHECK-M: add r7, sp, #4 +; CHECK-M: push {r4, r6, r7, lr} +; CHECK-M: add r7, sp, #8 ; CHECK-M: mov r4, sp ; CHECK-M: bic r4, r4, #7 ; CHECK-M: mov sp, r4 ; CHECK-M: blx _bar -; CHECK-M: subs r4, r7, #4 +; CHECK-M: sub.w r4, r7, #8 ; CHECK-M: mov sp, r4 -; CHECK-M: pop {r4, r7, pc} +; CHECK-M: pop {r4, r6, r7, pc} call arm_aapcscc void @bar() ret void @@ -88,13 +88,13 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" { define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" { ; CHECK-A-LABEL: undef_fn: -; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr} -; CHECK-A: add r11, sp, #16 -; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} +; CHECK-A: add r11, sp, #20 +; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; [...] -; CHECK-A: sub sp, r11, #16 -; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr} +; CHECK-A: sub sp, r11, #20 +; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: subs pc, lr, #0 call void @bar() @@ -103,13 +103,13 @@ define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" { define arm_aapcscc void @abort_fn() alignstack(8) "interrupt"="ABORT" { ; CHECK-A-LABEL: abort_fn: -; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr} -; CHECK-A: add r11, sp, #16 -; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} +; CHECK-A: add r11, sp, #20 +; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; [...] -; CHECK-A: sub sp, r11, #16 -; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr} +; CHECK-A: sub sp, r11, #20 +; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: subs pc, lr, #4 call void @bar() diff --git a/test/CodeGen/ARM/segmented-stacks-dynamic.ll b/test/CodeGen/ARM/segmented-stacks-dynamic.ll index 77c62de0cfd..86f8ff8dd90 100644 --- a/test/CodeGen/ARM/segmented-stacks-dynamic.ll +++ b/test/CodeGen/ARM/segmented-stacks-dynamic.ll @@ -29,7 +29,7 @@ false: ; ARM-linux-NEXT: cmp r4, r5 ; ARM-linux-NEXT: blo .LBB0_2 -; ARM-linux: mov r4, #24 +; ARM-linux: mov r4, #16 ; ARM-linux-NEXT: mov r5, #0 ; ARM-linux-NEXT: stmdb sp!, {lr} ; ARM-linux-NEXT: bl __morestack @@ -49,7 +49,7 @@ false: ; ARM-android-NEXT: cmp r4, r5 ; ARM-android-NEXT: blo .LBB0_2 -; ARM-android: mov r4, #24 +; ARM-android: mov r4, #16 ; ARM-android-NEXT: mov r5, #0 ; ARM-android-NEXT: stmdb sp!, {lr} ; ARM-android-NEXT: bl __morestack -- 2.34.1