From b5041b30851b1173170a8d281b2e9571a2a04bdd Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Wed, 13 Feb 2008 07:06:12 +0000 Subject: [PATCH] readme updates git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47051 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/README_ALTIVEC.txt | 9 +++++++++ lib/Target/X86/README-SSE.txt | 11 +++++++++++ 2 files changed, 20 insertions(+) diff --git a/lib/Target/PowerPC/README_ALTIVEC.txt b/lib/Target/PowerPC/README_ALTIVEC.txt index 143804da07f..461b4123c79 100644 --- a/lib/Target/PowerPC/README_ALTIVEC.txt +++ b/lib/Target/PowerPC/README_ALTIVEC.txt @@ -177,3 +177,12 @@ which prevents the vnot pattern from matching. //===----------------------------------------------------------------------===// + +An alternative to the store/store/load approach for illegal insert element +lowering would be: + +1. store element to any ol' slot +2. lvx the slot +3. lvsl 0; splat index; vcmpeq to generate a select mask +4. lvsl slot + x; vperm to rotate result into correct slot +5. vsel result together. diff --git a/lib/Target/X86/README-SSE.txt b/lib/Target/X86/README-SSE.txt index d9a03a3610c..197dae38c6f 100644 --- a/lib/Target/X86/README-SSE.txt +++ b/lib/Target/X86/README-SSE.txt @@ -781,3 +781,14 @@ any number of 0.0 simultaneously. Currently we only use it for simple insertions. See comments in LowerINSERT_VECTOR_ELT_SSE4. + +//===---------------------------------------------------------------------===// + +On a random note, SSE2 should declare insert/extract of 2 x f64 as legal, not +Custom. All combinations of insert/extract reg-reg, reg-mem, and mem-reg are +legal, it'll just take a few extra patterns written in the .td file. + +Note: this is not a code quality issue; the custom lowered code happens to be +right, but we shouldn't have to custom lower anything. This is probably related +to <2 x i64> ops being so bad. + -- 2.34.1