From af4bb57907a86d46e9a02dd7c6fea7a4dbc0eacf Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 6 Nov 2015 17:54:47 +0000 Subject: [PATCH] AMDGPU: Fix hardcoded alignment of spill. Instead of forcing 4 alignment when spilled, set register class alignments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252322 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIInstrInfo.cpp | 3 +-- lib/Target/AMDGPU/SIRegisterInfo.td | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index 9068c177878..d6cfcb5c47e 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -567,8 +567,7 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } if (Opcode != -1) { - unsigned Align = 4; - FrameInfo->setObjectAlignment(FrameIndex, Align); + unsigned Align = FrameInfo->getObjectAlignment(FrameIndex); unsigned Size = FrameInfo->getObjectSize(FrameIndex); MachinePointerInfo PtrInfo diff --git a/lib/Target/AMDGPU/SIRegisterInfo.td b/lib/Target/AMDGPU/SIRegisterInfo.td index f7abe53d828..e28dd2fdf91 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/lib/Target/AMDGPU/SIRegisterInfo.td @@ -187,50 +187,50 @@ def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI) >; -def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 64, (add SGPR_64Regs)>; +def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)>; -def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 64, +def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32, (add SGPR_64, VCC, EXEC, FLAT_SCR) >; -def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 128, (add SGPR_128)> { +def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 32, (add SGPR_128)> { // Requires 2 s_mov_b64 to copy let CopyCost = 2; } -def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)> { +def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add SGPR_256)> { // Requires 4 s_mov_b64 to copy let CopyCost = 4; } -def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)> { +def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 32, (add SGPR_512)> { // Requires 8 s_mov_b64 to copy let CopyCost = 8; } // Register class for all vector registers (VGPRs + Interploation Registers) -def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)> { +def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 32, (add VGPR_64)> { // Requires 2 v_mov_b32 to copy let CopyCost = 2; } -def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> { +def VReg_96 : RegisterClass<"AMDGPU", [untyped], 32, (add VGPR_96)> { let Size = 96; // Requires 3 v_mov_b32 to copy let CopyCost = 3; } -def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)> { +def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 32, (add VGPR_128)> { // Requires 4 v_mov_b32 to copy let CopyCost = 4; } -def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)> { +def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add VGPR_256)> { let CopyCost = 8; } -def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)> { +def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> { let CopyCost = 16; } @@ -274,7 +274,7 @@ def SCSrc_32 : RegInlineOperand { def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>; -def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 64, (add VReg_64, SReg_64)> { +def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> { let CopyCost = 2; } -- 2.34.1