From ad0a4c0be927e5aeac2955ef119aa2021e050be1 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 19 Jun 2007 00:06:08 +0000 Subject: [PATCH] New test case: identity operation of RHS / LHS of a VECTOR_SHUFFLE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37637 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/vec_shuffle-11.ll | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 test/CodeGen/X86/vec_shuffle-11.ll diff --git a/test/CodeGen/X86/vec_shuffle-11.ll b/test/CodeGen/X86/vec_shuffle-11.ll new file mode 100644 index 00000000000..553088fad92 --- /dev/null +++ b/test/CodeGen/X86/vec_shuffle-11.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep mov + +define <4 x i32> @test() { + %tmp131 = call <2 x i64> @llvm.x86.sse2.psrl.dq( <2 x i64> < i64 -1, i64 -1 >, i32 96 ) ; <<2 x i64>> [#uses=1] + %tmp137 = bitcast <2 x i64> %tmp131 to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp138 = and <4 x i32> %tmp137, bitcast (<2 x i64> < i64 -1, i64 -1 > to <4 x i32>) ; <<4 x i32>> [#uses=1] + ret <4 x i32> %tmp138 +} + +declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) -- 2.34.1