From ab695889c67fb499bd902e8a969d0ff02ce66788 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Wed, 21 Jul 2010 22:26:11 +0000 Subject: [PATCH] Baby steps towards ARM fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMFastISel.cpp | 71 ++++++++++++++++++++++++++++++ lib/Target/ARM/ARMISelLowering.cpp | 6 +++ lib/Target/ARM/ARMISelLowering.h | 9 ++++ lib/Target/ARM/CMakeLists.txt | 1 + lib/Target/ARM/Makefile | 3 +- test/CodeGen/ARM/fast-isel.ll | 15 +++++++ 6 files changed, 104 insertions(+), 1 deletion(-) create mode 100644 lib/Target/ARM/ARMFastISel.cpp create mode 100644 test/CodeGen/ARM/fast-isel.ll diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp new file mode 100644 index 00000000000..3e79d149e8a --- /dev/null +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -0,0 +1,71 @@ +//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the ARM-specific support for the FastISel class. Some +// of the target-specific code is generated by tablegen in the file +// ARMGenFastISel.inc, which is #included here. +// +//===----------------------------------------------------------------------===// + +#include "ARM.h" +#include "ARMRegisterInfo.h" +#include "ARMTargetMachine.h" +#include "ARMSubtarget.h" +#include "llvm/CallingConv.h" +#include "llvm/DerivedTypes.h" +#include "llvm/GlobalVariable.h" +#include "llvm/Instructions.h" +#include "llvm/IntrinsicInst.h" +#include "llvm/CodeGen/Analysis.h" +#include "llvm/CodeGen/FastISel.h" +#include "llvm/CodeGen/FunctionLoweringInfo.h" +#include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/CallSite.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/GetElementPtrTypeIterator.h" +#include "llvm/Target/TargetOptions.h" +using namespace llvm; + +namespace { + +class ARMFastISel : public FastISel { + + /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can + /// make the right decision when generating code for different targets. + const ARMSubtarget *Subtarget; + + public: + explicit ARMFastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) { + Subtarget = &TM.getSubtarget(); + } + + virtual bool TargetSelectInstruction(const Instruction *I); + + #include "ARMGenFastISel.inc" + + }; + +} // end anonymous namespace + +// #include "ARMGenCallingConv.inc" + +bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { + switch (I->getOpcode()) { + default: break; + } + return false; +} + +namespace llvm { + llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) { + return new ARMFastISel(funcInfo); + } +} diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 5888c1bf38a..9e5dd028962 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -694,6 +694,12 @@ TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { return TargetLowering::getRegClassFor(VT); } +// Create a fast isel object. +FastISel * +ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { + return ARM::createFastISel(funcInfo); +} + /// getFunctionAlignment - Return the Log2 alignment of this function. unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { return getTargetMachine().getSubtarget().isThumb() ? 1 : 2; diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 332b7a73be5..05d7d5f1cf1 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -17,6 +17,7 @@ #include "ARMSubtarget.h" #include "llvm/Target/TargetLowering.h" +#include "llvm/CodeGen/FastISel.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/CallingConvLower.h" #include @@ -261,6 +262,10 @@ namespace llvm { /// getFunctionAlignment - Return the Log2 alignment of this function. virtual unsigned getFunctionAlignment(const Function *F) const; + /// createFastISel - This method returns a target specific FastISel object, + /// or null if the target does not support "fast" ISel. + virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; + Sched::Preference getSchedulingPreference(SDNode *N) const; bool isShuffleMaskLegal(const SmallVectorImpl &M, EVT VT) const; @@ -387,6 +392,10 @@ namespace llvm { unsigned BinOpcode) const; }; + + namespace ARM { + FastISel *createFastISel(FunctionLoweringInfo &funcInfo); + } } #endif // ARMISELLOWERING_H diff --git a/lib/Target/ARM/CMakeLists.txt b/lib/Target/ARM/CMakeLists.txt index 41d2f23d618..28f440a767b 100644 --- a/lib/Target/ARM/CMakeLists.txt +++ b/lib/Target/ARM/CMakeLists.txt @@ -11,6 +11,7 @@ tablegen(ARMGenDAGISel.inc -gen-dag-isel) tablegen(ARMGenCallingConv.inc -gen-callingconv) tablegen(ARMGenSubtarget.inc -gen-subtarget) tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info) +tablegen(ARMFastISel.inc -gen-fast-isel) add_llvm_target(ARMCodeGen ARMAsmPrinter.cpp diff --git a/lib/Target/ARM/Makefile b/lib/Target/ARM/Makefile index 9e3ff29e07c..027618707d3 100644 --- a/lib/Target/ARM/Makefile +++ b/lib/Target/ARM/Makefile @@ -17,7 +17,8 @@ BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \ ARMGenInstrInfo.inc ARMGenAsmWriter.inc \ ARMGenDAGISel.inc ARMGenSubtarget.inc \ ARMGenCodeEmitter.inc ARMGenCallingConv.inc \ - ARMGenDecoderTables.inc ARMGenEDInfo.inc + ARMGenDecoderTables.inc ARMGenEDInfo.inc \ + ARMGenFastISel.inc DIRS = AsmPrinter AsmParser Disassembler TargetInfo diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll new file mode 100644 index 00000000000..c691cbefdb4 --- /dev/null +++ b/test/CodeGen/ARM/fast-isel.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -fast-isel -fast-isel-abort -march=arm + +; Very basic fast-isel functionality. + +define i32 @add(i32 %a, i32 %b) nounwind ssp { +entry: + %a.addr = alloca i32, align 4 + %b.addr = alloca i32, align 4 + store i32 %a, i32* %a.addr + store i32 %b, i32* %b.addr + %tmp = load i32* %a.addr + %tmp1 = load i32* %b.addr + %add = add nsw i32 %tmp, %tmp1 + ret i32 %add +} -- 2.34.1