From a8e1cda622221fabdfe86f583d378badfbd249f2 Mon Sep 17 00:00:00 2001
From: Adam Nemet <anemet@apple.com>
Date: Thu, 7 Aug 2014 23:53:38 +0000
Subject: [PATCH] [AVX512] Add zero-masking variant to AVX512_masking
 multiclass

This completes one item from the todo-list of r215125 "Generate masking
instruction variants with tablegen".

The AddedComplexity is needed just like for the k variant.

Added a codegen test based on valignq.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215173 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86InstrAVX512.td   | 14 ++++++++++++--
 test/CodeGen/X86/avx512-shuffle.ll |  9 +++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td
index a62e926629e..eaf52536c5a 100644
--- a/lib/Target/X86/X86InstrAVX512.td
+++ b/lib/Target/X86/X86InstrAVX512.td
@@ -1,7 +1,7 @@
 multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
                               string OpcodeStr,
                               string AttSrcAsm, string IntelSrcAsm,
-                              dag RHS,
+                              dag RHS, ValueType OpVT,
                               RegisterClass RC, RegisterClass KRC> {
   def NAME: AVX512<O, F, Outs, Ins,
                        OpcodeStr#" \t{"#AttSrcAsm#", $dst|"#
@@ -17,6 +17,16 @@ multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
                        [(set RC:$dst,
                              (vselect KRC:$mask, RHS, RC:$src0))]>,
               EVEX_K;
+  let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
+    def NAME#kz: AVX512<O, F, Outs,
+                       !con((ins KRC:$mask), Ins),
+                       OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
+                                      "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
+                       [(set RC:$dst,
+                             (vselect KRC:$mask, RHS,
+                                      (OpVT (bitconvert
+                                              (v16i32 immAllZerosV)))))]>,
+              EVEX_KZ;
 }
 
 // Bitcasts between 512-bit vector types. Return the original type since
@@ -4491,7 +4501,7 @@ multiclass avx512_valign<string Suffix, RegisterClass RC, RegisterClass KRC,
                      "$src3, $src2, $src1", "$src1, $src2, $src3",
                      (IntVT (X86VAlign RC:$src2, RC:$src1,
                                        (i8 imm:$src3))),
-                     RC, KRC>,
+                     IntVT, RC, KRC>,
              AVX512AIi8Base, EVEX_4V;
 
   // Also match valign of packed floats.
diff --git a/test/CodeGen/X86/avx512-shuffle.ll b/test/CodeGen/X86/avx512-shuffle.ll
index a4aa87a2ea9..bae99d97b21 100644
--- a/test/CodeGen/X86/avx512-shuffle.ll
+++ b/test/CodeGen/X86/avx512-shuffle.ll
@@ -216,6 +216,15 @@ define <8 x i64> @test16k(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask)
   ret <8 x i64> %res
 }
 
+; CHECK-LABEL: test16kz
+; CHECK: valignq $2, %zmm0, %zmm1, %zmm0 {%k1} {z} ## encoding: [0x62,0xf3,0xf5,0xc9,0x03,0xc0,0x02]
+define <8 x i64> @test16kz(<8 x i64> %a, <8 x i64> %b, i8 %mask) nounwind {
+  %c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
+  %m = bitcast i8 %mask to <8 x i1>
+  %res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> zeroinitializer
+  ret <8 x i64> %res
+}
+
 ; CHECK-LABEL: test17
 ; CHECK: vshufpd $19, %zmm1, %zmm0
 ; CHECK: ret
-- 
2.34.1