From a80ff266885a464b9270a86462dc01d41258d7d8 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 3 Sep 2014 11:41:21 +0000 Subject: [PATCH] Add override to overriden virtual methods, remove virtual keywords. No functionality change. Changes made by clang-tidy + some manual cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217028 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/MC/MCObjectStreamer.h | 2 +- include/llvm/Support/CrashRecoveryContext.h | 8 ++----- include/llvm/Target/TargetInstrInfo.h | 2 +- lib/Analysis/ScopedNoAliasAA.cpp | 24 +++++++++---------- .../RuntimeDyld/RuntimeDyldMachO.h | 3 ++- .../Targets/RuntimeDyldMachOAArch64.h | 2 +- .../RuntimeDyld/Targets/RuntimeDyldMachOARM.h | 2 +- .../Targets/RuntimeDyldMachOI386.h | 2 +- .../Targets/RuntimeDyldMachOX86_64.h | 2 +- lib/MC/MCMachOStreamer.cpp | 4 ++-- lib/Target/AArch64/AArch64ISelLowering.h | 2 +- lib/Target/AArch64/AArch64InstrInfo.cpp | 2 +- lib/Target/AArch64/AArch64InstrInfo.h | 12 +++++----- .../AArch64/InstPrinter/AArch64InstPrinter.h | 5 ++-- lib/Target/ARM/ARMSubtarget.h | 2 +- lib/Target/Hexagon/HexagonSubtarget.h | 16 ++++++++----- lib/Target/Mips/MipsTargetStreamer.h | 4 ++-- lib/Target/NVPTX/NVPTXISelLowering.h | 4 +--- lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp | 2 +- .../PowerPC/Disassembler/PPCDisassembler.cpp | 10 ++++---- .../MCTargetDesc/PPCELFObjectWriter.cpp | 20 +++------------- .../MCTargetDesc/PPCMachObjectWriter.cpp | 2 +- lib/Target/R600/AMDGPUISelLowering.h | 6 ++--- lib/Target/R600/AMDGPUInstrInfo.h | 5 ---- lib/Target/R600/AMDGPUPromoteAlloca.cpp | 8 +++---- lib/Target/R600/AMDGPURegisterInfo.h | 2 +- lib/Target/R600/AMDGPUTargetMachine.cpp | 2 +- lib/Target/R600/AMDGPUTargetMachine.h | 4 +++- lib/Target/R600/R600InstrInfo.h | 2 +- lib/Target/R600/SIInstrInfo.h | 2 +- .../XCore/Disassembler/XCoreDisassembler.cpp | 11 ++++----- 31 files changed, 73 insertions(+), 101 deletions(-) diff --git a/include/llvm/MC/MCObjectStreamer.h b/include/llvm/MC/MCObjectStreamer.h index 8d37c85b058..a3a95fb5367 100644 --- a/include/llvm/MC/MCObjectStreamer.h +++ b/include/llvm/MC/MCObjectStreamer.h @@ -126,7 +126,7 @@ public: void EmitZeros(uint64_t NumBytes) override; void FinishImpl() override; - virtual bool mayHaveInstructions() const { + bool mayHaveInstructions() const override { return getCurrentSectionData()->hasInstructions(); } }; diff --git a/include/llvm/Support/CrashRecoveryContext.h b/include/llvm/Support/CrashRecoveryContext.h index 3869ebdc4a9..f1e636d8ecc 100644 --- a/include/llvm/Support/CrashRecoveryContext.h +++ b/include/llvm/Support/CrashRecoveryContext.h @@ -166,9 +166,7 @@ public: : CrashRecoveryContextCleanupBase< CrashRecoveryContextDeleteCleanup, T>(context, resource) {} - virtual void recoverResources() { - delete this->resource; - } + void recoverResources() override { delete this->resource; } }; template @@ -181,9 +179,7 @@ public: : CrashRecoveryContextCleanupBase, T>(context, resource) {} - virtual void recoverResources() { - this->resource->Release(); - } + void recoverResources() override { this->resource->Release(); } }; template > diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index ffe30ea232e..f9ebf706797 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -688,7 +688,7 @@ public: } /// useMachineCombiner - return true when a target supports MachineCombiner - virtual bool useMachineCombiner(void) const { return false; } + virtual bool useMachineCombiner() const { return false; } protected: /// foldMemoryOperandImpl - Target-dependent implementation for diff --git a/lib/Analysis/ScopedNoAliasAA.cpp b/lib/Analysis/ScopedNoAliasAA.cpp index d090227d318..e6f24dd879d 100644 --- a/lib/Analysis/ScopedNoAliasAA.cpp +++ b/lib/Analysis/ScopedNoAliasAA.cpp @@ -80,15 +80,13 @@ public: initializeScopedNoAliasAAPass(*PassRegistry::getPassRegistry()); } - virtual void initializePass() { - InitializeAliasAnalysis(this); - } + void initializePass() override { InitializeAliasAnalysis(this); } /// getAdjustedAnalysisPointer - This method is used when a pass implements /// an analysis interface through multiple inheritance. If needed, it /// should override this to adjust the this pointer as needed for the /// specified pass info. - virtual void *getAdjustedAnalysisPointer(const void *PI) { + void *getAdjustedAnalysisPointer(const void *PI) override { if (PI == &AliasAnalysis::ID) return (AliasAnalysis*)this; return this; @@ -100,15 +98,15 @@ protected: SmallPtrSetImpl &Nodes) const; private: - virtual void getAnalysisUsage(AnalysisUsage &AU) const; - virtual AliasResult alias(const Location &LocA, const Location &LocB); - virtual bool pointsToConstantMemory(const Location &Loc, bool OrLocal); - virtual ModRefBehavior getModRefBehavior(ImmutableCallSite CS); - virtual ModRefBehavior getModRefBehavior(const Function *F); - virtual ModRefResult getModRefInfo(ImmutableCallSite CS, - const Location &Loc); - virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, - ImmutableCallSite CS2); + void getAnalysisUsage(AnalysisUsage &AU) const override; + AliasResult alias(const Location &LocA, const Location &LocB) override; + bool pointsToConstantMemory(const Location &Loc, bool OrLocal) override; + ModRefBehavior getModRefBehavior(ImmutableCallSite CS) override; + ModRefBehavior getModRefBehavior(const Function *F) override; + ModRefResult getModRefInfo(ImmutableCallSite CS, + const Location &Loc) override; + ModRefResult getModRefInfo(ImmutableCallSite CS1, + ImmutableCallSite CS2) override; }; } // End of anonymous namespace diff --git a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h index c017c2225b4..8a00c0bdea0 100644 --- a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h +++ b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h @@ -140,7 +140,8 @@ private: public: RuntimeDyldMachOCRTPBase(RTDyldMemoryManager *mm) : RuntimeDyldMachO(mm) {} - void finalizeLoad(ObjectImage &ObjImg, ObjSectionToIDMap &SectionMap) { + void finalizeLoad(ObjectImage &ObjImg, + ObjSectionToIDMap &SectionMap) override { unsigned EHFrameSID = RTDYLD_INVALID_SECTION_ID; unsigned TextSID = RTDYLD_INVALID_SECTION_ID; unsigned ExceptTabSID = RTDYLD_INVALID_SECTION_ID; diff --git a/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h b/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h index 062d402610a..01d84f5c339 100644 --- a/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h +++ b/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h @@ -296,7 +296,7 @@ public: return ++RelI; } - void resolveRelocation(const RelocationEntry &RE, uint64_t Value) { + void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override { DEBUG(dumpRelocationToResolve(RE, Value)); const SectionEntry &Section = Sections[RE.SectionID]; diff --git a/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h b/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h index 395ffaa5863..69ae44d4d65 100644 --- a/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h +++ b/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h @@ -78,7 +78,7 @@ public: return ++RelI; } - void resolveRelocation(const RelocationEntry &RE, uint64_t Value) { + void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override { DEBUG(dumpRelocationToResolve(RE, Value)); const SectionEntry &Section = Sections[RE.SectionID]; uint8_t *LocalAddress = Section.Address + RE.Offset; diff --git a/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h b/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h index 10b19019a74..21378ce79d2 100644 --- a/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h +++ b/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h @@ -75,7 +75,7 @@ public: return ++RelI; } - void resolveRelocation(const RelocationEntry &RE, uint64_t Value) { + void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override { DEBUG(dumpRelocationToResolve(RE, Value)); const SectionEntry &Section = Sections[RE.SectionID]; diff --git a/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h b/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h index 425695cca9c..0585b4caf1e 100644 --- a/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h +++ b/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h @@ -61,7 +61,7 @@ public: return ++RelI; } - void resolveRelocation(const RelocationEntry &RE, uint64_t Value) { + void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override { DEBUG(dumpRelocationToResolve(RE, Value)); const SectionEntry &Section = Sections[RE.SectionID]; uint8_t *LocalAddress = Section.Address + RE.Offset; diff --git a/lib/MC/MCMachOStreamer.cpp b/lib/MC/MCMachOStreamer.cpp index 9e8bc942e49..23b89759a2c 100644 --- a/lib/MC/MCMachOStreamer.cpp +++ b/lib/MC/MCMachOStreamer.cpp @@ -90,8 +90,8 @@ public: unsigned ByteAlignment) override; void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = nullptr, uint64_t Size = 0, unsigned ByteAlignment = 0) override; - virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol, - uint64_t Size, unsigned ByteAlignment = 0) override; + void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol, uint64_t Size, + unsigned ByteAlignment = 0) override; void EmitFileDirective(StringRef Filename) override { // FIXME: Just ignore the .file; it isn't important enough to fail the diff --git a/lib/Target/AArch64/AArch64ISelLowering.h b/lib/Target/AArch64/AArch64ISelLowering.h index 376430a2f67..34f2d73dd23 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.h +++ b/lib/Target/AArch64/AArch64ISelLowering.h @@ -426,7 +426,7 @@ private: SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, - std::vector *Created) const; + std::vector *Created) const override; ConstraintType getConstraintType(const std::string &Constraint) const override; diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp index 1aa511dc548..7a94d1314f4 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -2206,7 +2206,7 @@ void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { NopInst.addOperand(MCOperand::CreateImm(0)); } /// useMachineCombiner - return true when a target supports MachineCombiner -bool AArch64InstrInfo::useMachineCombiner(void) const { +bool AArch64InstrInfo::useMachineCombiner() const { // AArch64 supports the combiner return true; } diff --git a/lib/Target/AArch64/AArch64InstrInfo.h b/lib/Target/AArch64/AArch64InstrInfo.h index 3ab1b9ce571..876ea0e6d2d 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.h +++ b/lib/Target/AArch64/AArch64InstrInfo.h @@ -161,20 +161,20 @@ public: /// for an instruction chain ending in . All potential patterns are /// listed /// in the array. - virtual bool hasPattern( - MachineInstr &Root, - SmallVectorImpl &Pattern) const; + bool hasPattern(MachineInstr &Root, + SmallVectorImpl &Pattern) + const override; /// genAlternativeCodeSequence - when hasPattern() finds a pattern /// this function generates the instructions that could replace the /// original code sequence - virtual void genAlternativeCodeSequence( + void genAlternativeCodeSequence( MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, - DenseMap &InstrIdxForVirtReg) const; + DenseMap &InstrIdxForVirtReg) const override; /// useMachineCombiner - AArch64 supports MachineCombiner - virtual bool useMachineCombiner(void) const; + bool useMachineCombiner() const override; bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; private: diff --git a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h index 4e13dcea24e..5f51621d674 100644 --- a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h +++ b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h @@ -127,8 +127,9 @@ public: void printInstruction(const MCInst *MI, raw_ostream &O) override; bool printAliasInstr(const MCInst *MI, raw_ostream &O) override; - virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); + void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, + raw_ostream &O) override; StringRef getRegName(unsigned RegNo) const override { return getRegisterName(RegNo); } diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index 3cbeae88cc9..2fdfc35a528 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -437,7 +437,7 @@ public: /// getInstrItins - Return the instruction itineraries based on subtarget /// selection. - const InstrItineraryData *getInstrItineraryData() const { + const InstrItineraryData *getInstrItineraryData() const override { return &InstrItins; } diff --git a/lib/Target/Hexagon/HexagonSubtarget.h b/lib/Target/Hexagon/HexagonSubtarget.h index e7cbf1b62e7..10776ae0eb3 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.h +++ b/lib/Target/Hexagon/HexagonSubtarget.h @@ -58,19 +58,23 @@ public: /// getInstrItins - Return the instruction itineraries based on subtarget /// selection. - const InstrItineraryData *getInstrItineraryData() const { + const InstrItineraryData *getInstrItineraryData() const override { return &InstrItins; } const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; } - const HexagonRegisterInfo *getRegisterInfo() const { + const HexagonRegisterInfo *getRegisterInfo() const override { return &InstrInfo.getRegisterInfo(); } - const HexagonTargetLowering *getTargetLowering() const { return &TLInfo; } - const HexagonFrameLowering *getFrameLowering() const { + const HexagonTargetLowering *getTargetLowering() const override { + return &TLInfo; + } + const HexagonFrameLowering *getFrameLowering() const override { return &FrameLowering; } - const HexagonSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } - const DataLayout *getDataLayout() const { return &DL; } + const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override { + return &TSInfo; + } + const DataLayout *getDataLayout() const override { return &DL; } HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); diff --git a/lib/Target/Mips/MipsTargetStreamer.h b/lib/Target/Mips/MipsTargetStreamer.h index 8b87aefa91a..d689c343fad 100644 --- a/lib/Target/Mips/MipsTargetStreamer.h +++ b/lib/Target/Mips/MipsTargetStreamer.h @@ -163,7 +163,7 @@ public: void emitDirectiveSetDsp() override; // PIC support - virtual void emitDirectiveCpload(unsigned RegNo); + void emitDirectiveCpload(unsigned RegNo) override; void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override; @@ -209,7 +209,7 @@ public: void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override; // PIC support - virtual void emitDirectiveCpload(unsigned RegNo); + void emitDirectiveCpload(unsigned RegNo) override; void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override; diff --git a/lib/Target/NVPTX/NVPTXISelLowering.h b/lib/Target/NVPTX/NVPTXISelLowering.h index f4f2358c16d..d66d81a5316 100644 --- a/lib/Target/NVPTX/NVPTXISelLowering.h +++ b/lib/Target/NVPTX/NVPTXISelLowering.h @@ -505,9 +505,7 @@ public: bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const; - virtual bool isFMAFasterThanFMulAndFAdd(EVT) const { - return true; - } + bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; } private: const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here diff --git a/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp b/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp index 151aaf21999..324420d40c9 100644 --- a/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp +++ b/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp @@ -33,7 +33,7 @@ private: public: NVPTXReplaceImageHandles(); - bool runOnMachineFunction(MachineFunction &MF); + bool runOnMachineFunction(MachineFunction &MF) override; const char *getPassName() const override { return "NVPTX Replace Image Handles"; diff --git a/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index a2305a9efc7..048f2ad89f3 100644 --- a/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -29,12 +29,10 @@ public: virtual ~PPCDisassembler() {} // Override MCDisassembler. - virtual DecodeStatus getInstruction(MCInst &instr, - uint64_t &size, - const MemoryObject ®ion, - uint64_t address, - raw_ostream &vStream, - raw_ostream &cStream) const override; + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + const MemoryObject ®ion, uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; }; } // end anonymous namespace diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp index ca813176bd5..578f0c723a9 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -24,11 +24,7 @@ namespace { public: PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI); - virtual ~PPCELFObjectWriter(); protected: - virtual unsigned getRelocTypeInner(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel) const; unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const override; @@ -42,9 +38,6 @@ PPCELFObjectWriter::PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI) Is64Bit ? ELF::EM_PPC64 : ELF::EM_PPC, /*HasRelocationAddend*/ true) {} -PPCELFObjectWriter::~PPCELFObjectWriter() { -} - static MCSymbolRefExpr::VariantKind getAccessVariant(const MCValue &Target, const MCFixup &Fixup) { const MCExpr *Expr = Fixup.getValue(); @@ -73,10 +66,9 @@ static MCSymbolRefExpr::VariantKind getAccessVariant(const MCValue &Target, llvm_unreachable("unknown PPCMCExpr kind"); } -unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel) const -{ +unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel) const { MCSymbolRefExpr::VariantKind Modifier = getAccessVariant(Target, Fixup); // determine the type of the relocation @@ -400,12 +392,6 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target, return Type; } -unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel) const { - return getRelocTypeInner(Target, Fixup, IsPCRel); -} - bool PPCELFObjectWriter::needsRelocateWithSymbol(const MCSymbolData &SD, unsigned Type) const { switch (Type) { diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp index cff27baeb5e..2d5857fc631 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp @@ -80,7 +80,7 @@ static unsigned getFixupKindLog2Size(unsigned Kind) { } /// Translates generic PPC fixup kind to Mach-O/PPC relocation type enum. -/// Outline based on PPCELFObjectWriter::getRelocTypeInner(). +/// Outline based on PPCELFObjectWriter::GetRelocType(). static unsigned getRelocType(const MCValue &Target, const MCFixupKind FixupKind, // from // Fixup.getKind() diff --git a/lib/Target/R600/AMDGPUISelLowering.h b/lib/Target/R600/AMDGPUISelLowering.h index 3dc703520cb..fc4c006a0e5 100644 --- a/lib/Target/R600/AMDGPUISelLowering.h +++ b/lib/Target/R600/AMDGPUISelLowering.h @@ -153,10 +153,8 @@ public: const SelectionDAG &DAG, unsigned Depth = 0) const override; - virtual unsigned ComputeNumSignBitsForTargetNode( - SDValue Op, - const SelectionDAG &DAG, - unsigned Depth = 0) const override; + unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, + unsigned Depth = 0) const override; /// \brief Helper function that adds Reg to the LiveIn list of the DAG's /// MachineFunction. diff --git a/lib/Target/R600/AMDGPUInstrInfo.h b/lib/Target/R600/AMDGPUInstrInfo.h index bf8e23d58b2..9054ec66942 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.h +++ b/lib/Target/R600/AMDGPUInstrInfo.h @@ -73,11 +73,6 @@ public: LiveVariables *LV) const override; - virtual void copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, - bool KillSrc) const = 0; - bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; void storeRegToStackSlot(MachineBasicBlock &MBB, diff --git a/lib/Target/R600/AMDGPUPromoteAlloca.cpp b/lib/Target/R600/AMDGPUPromoteAlloca.cpp index 218750d445e..620925a62b1 100644 --- a/lib/Target/R600/AMDGPUPromoteAlloca.cpp +++ b/lib/Target/R600/AMDGPUPromoteAlloca.cpp @@ -36,11 +36,9 @@ class AMDGPUPromoteAlloca : public FunctionPass, public: AMDGPUPromoteAlloca(const AMDGPUSubtarget &st) : FunctionPass(ID), ST(st), LocalMemAvailable(0) { } - virtual bool doInitialization(Module &M); - virtual bool runOnFunction(Function &F); - virtual const char *getPassName() const { - return "AMDGPU Promote Alloca"; - } + bool doInitialization(Module &M) override; + bool runOnFunction(Function &F) override; + const char *getPassName() const override { return "AMDGPU Promote Alloca"; } void visitAlloca(AllocaInst &I); }; diff --git a/lib/Target/R600/AMDGPURegisterInfo.h b/lib/Target/R600/AMDGPURegisterInfo.h index 9f99decddca..f27576ab973 100644 --- a/lib/Target/R600/AMDGPURegisterInfo.h +++ b/lib/Target/R600/AMDGPURegisterInfo.h @@ -51,7 +51,7 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { unsigned getSubRegFromChannel(unsigned Channel) const; const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override; - virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, + void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override; unsigned getFrameRegister(const MachineFunction &MF) const override; diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index 890e2b776b2..1203cce54ec 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -80,7 +80,7 @@ public: return nullptr; } - virtual void addCodeGenPrepare(); + void addCodeGenPrepare() override; bool addPreISel() override; bool addInstSelector() override; bool addPreRegAlloc() override; diff --git a/lib/Target/R600/AMDGPUTargetMachine.h b/lib/Target/R600/AMDGPUTargetMachine.h index 725455c38be..ff581b5c9aa 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.h +++ b/lib/Target/R600/AMDGPUTargetMachine.h @@ -36,7 +36,9 @@ public: const AMDGPUSubtarget *getSubtargetImpl() const override { return &Subtarget; } - const AMDGPUIntrinsicInfo *getIntrinsicInfo() const { return &IntrinsicInfo; } + const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override { + return &IntrinsicInfo; + } TargetPassConfig *createPassConfig(PassManagerBase &PM) override; /// \brief Register R600 analysis passes with a pass manager. diff --git a/lib/Target/R600/R600InstrInfo.h b/lib/Target/R600/R600InstrInfo.h index adca8604457..6b646aa7f3c 100644 --- a/lib/Target/R600/R600InstrInfo.h +++ b/lib/Target/R600/R600InstrInfo.h @@ -206,7 +206,7 @@ namespace llvm { int getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const override { return 1;} - virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; + bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; /// \brief Reserve the registers that may be accesed using indirect addressing. void reserveIndirectRegisters(BitVector &Reserved, diff --git a/lib/Target/R600/SIInstrInfo.h b/lib/Target/R600/SIInstrInfo.h index b7aeb95142e..70682ff78d7 100644 --- a/lib/Target/R600/SIInstrInfo.h +++ b/lib/Target/R600/SIInstrInfo.h @@ -87,7 +87,7 @@ public: const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; - virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; + bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; unsigned commuteOpcode(unsigned Opcode) const; diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index 7fef7960a8f..b1d9ab82813 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -37,13 +37,10 @@ public: MCDisassembler(STI, Ctx) {} /// \brief See MCDisassembler. - virtual DecodeStatus getInstruction(MCInst &instr, - uint64_t &size, - const MemoryObject ®ion, - uint64_t address, - raw_ostream &vStream, - raw_ostream &cStream) const override; - + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + const MemoryObject ®ion, uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; }; } -- 2.34.1