From a002a91ad8eeb1b5382301acb7978ce986c67d05 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Fri, 18 Jul 2014 23:25:00 +0000 Subject: [PATCH] Make InstrInfo depend only upon the Subtarget getting passed in rather than the TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213425 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16InstrInfo.cpp | 9 +++--- lib/Target/Mips/Mips16InstrInfo.h | 2 +- lib/Target/Mips/MipsInstrInfo.cpp | 16 +++++----- lib/Target/Mips/MipsInstrInfo.h | 10 +++---- lib/Target/Mips/MipsSEInstrInfo.cpp | 46 ++++++++++++++--------------- lib/Target/Mips/MipsSEInstrInfo.h | 2 +- lib/Target/Mips/MipsSubtarget.cpp | 6 ++-- 7 files changed, 44 insertions(+), 47 deletions(-) diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index 3c207cb5de3..4dd9af24968 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -31,9 +31,8 @@ using namespace llvm; #define DEBUG_TYPE "mips16-instrinfo" -Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm) - : MipsInstrInfo(tm, Mips::Bimm16), - RI(*tm.getSubtargetImpl()) {} +Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI) + : MipsInstrInfo(STI, Mips::Bimm16), RI(STI) {} const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const { return RI; @@ -450,8 +449,8 @@ void Mips16InstrInfo::BuildAddiuSpImm BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm); } -const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) { - return new Mips16InstrInfo(TM); +const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) { + return new Mips16InstrInfo(STI); } bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg, diff --git a/lib/Target/Mips/Mips16InstrInfo.h b/lib/Target/Mips/Mips16InstrInfo.h index 0dc00461ccf..a004c567e6c 100644 --- a/lib/Target/Mips/Mips16InstrInfo.h +++ b/lib/Target/Mips/Mips16InstrInfo.h @@ -23,7 +23,7 @@ class Mips16InstrInfo : public MipsInstrInfo { const Mips16RegisterInfo RI; public: - explicit Mips16InstrInfo(MipsTargetMachine &TM); + explicit Mips16InstrInfo(const MipsSubtarget &STI); const MipsRegisterInfo &getRegisterInfo() const override; diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 1db89c65a9a..dcc0e24e080 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -30,15 +30,15 @@ using namespace llvm; // Pin the vtable to this file. void MipsInstrInfo::anchor() {} -MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr) - : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), - TM(tm), UncondBrOpc(UncondBr) {} +MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr) + : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), + Subtarget(STI), UncondBrOpc(UncondBr) {} -const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) { - if (TM.getSubtargetImpl()->inMips16Mode()) - return llvm::createMips16InstrInfo(TM); +const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) { + if (STI.inMips16Mode()) + return llvm::createMips16InstrInfo(STI); - return llvm::createMipsSEInstrInfo(TM); + return llvm::createMipsSEInstrInfo(STI); } bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const { @@ -156,7 +156,7 @@ unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { // Up to 2 branches are removed. // Note that indirect branches are not removed. - for(removed = 0; I != REnd && removed < 2; ++I, ++removed) + for (removed = 0; I != REnd && removed < 2; ++I, ++removed) if (!getAnalyzableBrOpc(I->getOpcode())) break; diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 742193f712c..bdf2fd37ed8 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -33,7 +33,7 @@ namespace llvm { class MipsInstrInfo : public MipsGenInstrInfo { virtual void anchor(); protected: - MipsTargetMachine &TM; + const MipsSubtarget &Subtarget; unsigned UncondBrOpc; public: @@ -46,9 +46,9 @@ public: BT_Indirect // One indirct branch. }; - explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc); + explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); - static const MipsInstrInfo *create(MipsTargetMachine &TM); + static const MipsInstrInfo *create(MipsSubtarget &STI); /// Branch Analysis bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, @@ -140,8 +140,8 @@ private: }; /// Create MipsInstrInfo objects. -const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM); -const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM); +const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); +const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); } diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index 26764611c50..69cb74cb1e4 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -24,11 +24,10 @@ using namespace llvm; -MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm) - : MipsInstrInfo(tm, - tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J), - RI(*tm.getSubtargetImpl()), - IsN64(tm.getSubtarget().isABI_N64()) {} +MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) + : MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B + : Mips::J), + RI(STI), IsN64(STI.isABI_N64()) {} const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { return RI; @@ -84,7 +83,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { unsigned Opc = 0, ZeroReg = 0; - bool isMicroMips = TM.getSubtarget().inMicroMipsMode(); + bool isMicroMips = Subtarget.inMicroMipsMode(); if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. if (Mips::GPR32RegClass.contains(SrcReg)) { @@ -265,7 +264,7 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { MachineBasicBlock &MBB = *MI->getParent(); - bool isMicroMips = TM.getSubtarget().inMicroMipsMode(); + bool isMicroMips = Subtarget.inMicroMipsMode(); unsigned Opc; switch(MI->getDesc().getOpcode()) { @@ -360,7 +359,7 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const MipsSubtarget &STI = TM.getSubtarget(); + const MipsSubtarget &STI = Subtarget; DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; @@ -380,7 +379,7 @@ MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned *NewImm) const { MipsAnalyzeImmediate AnalyzeImm; - const MipsSubtarget &STI = TM.getSubtarget(); + const MipsSubtarget &STI = Subtarget; MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); unsigned Size = STI.isABI_N64() ? 64 : 32; unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; @@ -429,8 +428,6 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const auto &Subtarget = TM.getSubtarget(); - if (Subtarget.isGP64bit()) BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64)) .addReg(Mips::RA_64); @@ -512,7 +509,6 @@ void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB, void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool FP64) const { - const MipsSubtarget &Subtarget = TM.getSubtarget(); unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); unsigned N = I->getOperand(2).getImm(); @@ -552,7 +548,6 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool FP64) const { - const MipsSubtarget &Subtarget = TM.getSubtarget(); unsigned DstReg = I->getOperand(0).getReg(); unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); @@ -612,28 +607,31 @@ void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, // This pseudo instruction is generated as part of the lowering of // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and // indirect jump to TargetReg - const MipsSubtarget &STI = TM.getSubtarget(); - unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; - unsigned SP = STI.isGP64bit() ? Mips::SP_64 : Mips::SP; - unsigned RA = STI.isGP64bit() ? Mips::RA_64 : Mips::RA; - unsigned T9 = STI.isGP64bit() ? Mips::T9_64 : Mips::T9; - unsigned ZERO = STI.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; + unsigned ADDU = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; + unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; + unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; + unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; + unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; unsigned OffsetReg = I->getOperand(0).getReg(); unsigned TargetReg = I->getOperand(1).getReg(); // addu $ra, $v0, $zero // addu $sp, $sp, $v1 // jr $ra (via RetRA) + const TargetMachine &TM = MBB.getParent()->getTarget(); if (TM.getRelocationModel() == Reloc::PIC_) BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9) - .addReg(TargetReg).addReg(ZERO); + .addReg(TargetReg) + .addReg(ZERO); BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA) - .addReg(TargetReg).addReg(ZERO); + .addReg(TargetReg) + .addReg(ZERO); BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP) - .addReg(SP).addReg(OffsetReg); + .addReg(SP) + .addReg(OffsetReg); expandRetRA(MBB, I); } -const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) { - return new MipsSEInstrInfo(TM); +const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) { + return new MipsSEInstrInfo(STI); } diff --git a/lib/Target/Mips/MipsSEInstrInfo.h b/lib/Target/Mips/MipsSEInstrInfo.h index 9ac94ce38f6..9576fef1bd9 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.h +++ b/lib/Target/Mips/MipsSEInstrInfo.h @@ -24,7 +24,7 @@ class MipsSEInstrInfo : public MipsInstrInfo { bool IsN64; public: - explicit MipsSEInstrInfo(MipsTargetMachine &TM); + explicit MipsSEInstrInfo(const MipsSubtarget &STI); const MipsRegisterInfo &getRegisterInfo() const override; diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index a03b5ca19e6..71332eb9eea 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -115,7 +115,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT), DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))), - TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*TM)), + TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)), FrameLowering(MipsFrameLowering::create(*TM, *this)), TLInfo(MipsTargetLowering::create(*TM)) { @@ -254,7 +254,7 @@ void MipsSubtarget::setHelperClassesMips16() { FrameLoweringSE.swap(FrameLowering); TLInfoSE.swap(TLInfo); if (!InstrInfo16) { - InstrInfo.reset(MipsInstrInfo::create(*TM)); + InstrInfo.reset(MipsInstrInfo::create(*this)); FrameLowering.reset(MipsFrameLowering::create(*TM, *this)); TLInfo.reset(MipsTargetLowering::create(*TM)); } else { @@ -272,7 +272,7 @@ void MipsSubtarget::setHelperClassesMipsSE() { FrameLowering16.swap(FrameLowering); TLInfo16.swap(TLInfo); if (!InstrInfoSE) { - InstrInfo.reset(MipsInstrInfo::create(*TM)); + InstrInfo.reset(MipsInstrInfo::create(*this)); FrameLowering.reset(MipsFrameLowering::create(*TM, *this)); TLInfo.reset(MipsTargetLowering::create(*TM)); } else { -- 2.34.1