From 9edb4236ccec1318e4463c29ec2280de7b1e439d Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Thu, 26 Nov 2015 16:35:41 +0000 Subject: [PATCH] [mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254164 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 59 +++++++------------ lib/Target/Mips/MicroMipsInstrInfo.td | 13 ----- lib/Target/Mips/Mips64InstrInfo.td | 53 +++++++++++++---- lib/Target/Mips/MipsDSPInstrInfo.td | 14 ++--- lib/Target/Mips/MipsInstrInfo.td | 65 ++++++++++++++++++--- test/MC/Mips/cnmips/invalid.s | 15 +++++ test/MC/Mips/dspr2/invalid.s | 15 ++++- test/MC/Mips/dspr2/valid.s | 3 + test/MC/Mips/eva/invalid.s | 11 ++++ test/MC/Mips/micromips-invalid.s | 27 +++++---- test/MC/Mips/micromips/invalid.s | 27 +++++++-- test/MC/Mips/micromips32r6/invalid.s | 26 ++++++--- test/MC/Mips/micromips64r6/invalid.s | 27 ++++++--- test/MC/Mips/mips32r2/invalid.s | 10 +++- test/MC/Mips/mips32r3/invalid.s | 10 +++- test/MC/Mips/mips32r5/invalid.s | 10 +++- test/MC/Mips/mips32r6/invalid.s | 10 +++- test/MC/Mips/mips64-alu-instructions.s | 4 +- test/MC/Mips/mips64r2/invalid.s | 12 +++- test/MC/Mips/mips64r3/invalid.s | 12 +++- test/MC/Mips/mips64r5/invalid.s | 12 +++- test/MC/Mips/mips64r6/invalid.s | 8 +++ test/MC/Mips/msa/invalid.s | 4 ++ 23 files changed, 312 insertions(+), 135 deletions(-) create mode 100644 test/MC/Mips/cnmips/invalid.s create mode 100644 test/MC/Mips/eva/invalid.s diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 32856550b70..44f665a86c6 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -928,12 +928,13 @@ public: Inst.addOperand(MCOperand::createReg(getHWRegsReg())); } - template + template void addConstantUImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); uint64_t Imm = getConstantImm() - Offset; Imm &= (1 << Bits) - 1; Imm += Offset; + Imm += AdjustOffset; Inst.addOperand(MCOperand::createImm(Imm)); } @@ -1034,8 +1035,10 @@ public: && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP); } - bool isUImm5Lsl2() const { - return (isImm() && isConstantImm() && isShiftedUInt<5, 2>(getConstantImm())); + template + bool isScaledUImm() const { + return isConstantImm() && + isShiftedUInt(getConstantImm()); } bool isRegList16() const { if (!isRegList()) @@ -1620,32 +1623,6 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, } break; - case Mips::CINS: - case Mips::CINS32: - case Mips::EXTS: - case Mips::EXTS32: - assert(MCID.getNumOperands() == 4 && "unexpected number of operands"); - // Check length - Opnd = Inst.getOperand(3); - if (!Opnd.isImm()) - return Error(IDLoc, "expected immediate operand kind"); - Imm = Opnd.getImm(); - if (Imm < 0 || Imm > 31) - return Error(IDLoc, "immediate operand value out of range"); - // Check position - Opnd = Inst.getOperand(2); - if (!Opnd.isImm()) - return Error(IDLoc, "expected immediate operand kind"); - Imm = Opnd.getImm(); - if (Imm < 0 || Imm > (Opcode == Mips::CINS || - Opcode == Mips::EXTS ? 63 : 31)) - return Error(IDLoc, "immediate operand value out of range"); - if (Imm > 31) { - Inst.setOpcode(Opcode == Mips::CINS ? Mips::CINS32 : Mips::EXTS32); - Inst.getOperand(2).setImm(Imm - 32); - } - break; - case Mips::SEQi: case Mips::SNEi: assert(MCID.getNumOperands() == 3 && "unexpected number of operands"); @@ -1909,16 +1886,6 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, if (Imm < 0 || Imm > 60 || (Imm % 4 != 0)) return Error(IDLoc, "immediate operand value out of range"); break; - case Mips::PREFX_MM: - case Mips::CACHE: - case Mips::PREF: - Opnd = Inst.getOperand(2); - if (!Opnd.isImm()) - return Error(IDLoc, "expected immediate operand kind"); - Imm = Opnd.getImm(); - if (!isUInt<5>(Imm)) - return Error(IDLoc, "immediate operand value out of range"); - break; case Mips::ADDIUPC_MM: MCOperand Opnd = Inst.getOperand(1); if (!Opnd.isImm()) @@ -3666,6 +3633,20 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_UImm4_0: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 4-bit unsigned immediate"); + case Match_UImm5_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 5-bit unsigned immediate"); + case Match_UImm5_32: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range 32 .. 63"); + case Match_UImm5_0_Report_UImm6: + // This is used on UImm5 operands that have a corresponding UImm5_32 + // operand to avoid confusing the user. + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 6-bit unsigned immediate"); + case Match_UImm5_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected both 7-bit unsigned immediate and multiple of 4"); } llvm_unreachable("Implement any new match types added!"); diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 5eb5a4d233b..175a9559e00 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -13,19 +13,6 @@ def simm12 : Operand { let DecoderMethod = "DecodeSimm12"; } -def MipsUimm5Lsl2AsmOperand : AsmOperandClass { - let Name = "Uimm5Lsl2"; - let RenderMethod = "addImmOperands"; - let ParserMethod = "parseImm"; - let PredicateMethod = "isUImm5Lsl2"; -} - -def uimm5_lsl2 : Operand { - let EncoderMethod = "getUImm5Lsl2Encoding"; - let DecoderMethod = "DecodeUImm5lsl2"; - let ParserMatchClass = MipsUimm5Lsl2AsmOperand; -} - def uimm6_lsl2 : Operand { let EncoderMethod = "getUImm6Lsl2Encoding"; let DecoderMethod = "DecodeUImm6Lsl2"; diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index ec0953cae03..0992186a087 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -16,10 +16,6 @@ //===----------------------------------------------------------------------===// // Unsigned Operand -def uimm5_64 : Operand { - let PrintMethod = "printUnsignedImm"; -} - def uimm16_64 : Operand { let PrintMethod = "printUnsignedImm"; } @@ -343,8 +339,8 @@ class SetCC64_I: } class CBranchBitNum shift = 1> : - InstSE<(outs), (ins RO:$rs, uimm5_64:$p, opnd:$offset), + RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> : + InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset), !strconcat(opstr, "\t$rs, $p, $offset"), [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)), bb:$offset)], II_BBIT, FrmI, opstr> { @@ -365,14 +361,17 @@ def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, ADD_FM<0x1c, 0x28>; // Branch on Bit Clear /+32 -def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd>, BBIT_FM<0x32>; -def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, 0x100000000>, +def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd, + uimm5_64_report_uimm6>, BBIT_FM<0x32>; +def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64, + 0x100000000>, BBIT_FM<0x36>; // Branch on Bit Set /+32 -def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd>, BBIT_FM<0x3a>; -def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, 0x100000000>, - BBIT_FM<0x3e>; +def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, + uimm5_64_report_uimm6>, BBIT_FM<0x3a>; +def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64, + 0x100000000>, BBIT_FM<0x3e>; // Multiply Doubleword to GPR let Defs = [HI0, LO0, P0, P1, P2] in @@ -634,6 +633,38 @@ def : MipsInstAlias<"syncw", (SYNC 0x4), 0>; def : MipsInstAlias<"syncws", (SYNC 0x5), 0>; } +// cnMIPS Aliases. + +// bbit* with $p 32-63 converted to bbit*32 with $p 0-31 +def : MipsInstAlias<"bbit0 $rs, $p, $offset", + (BBIT032 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, + brtarget:$offset), 0>, + ASE_CNMIPS; +def : MipsInstAlias<"bbit1 $rs, $p, $offset", + (BBIT132 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, + brtarget:$offset), 0>, + ASE_CNMIPS; + +// exts with $pos 32-63 in converted to exts32 with $pos 0-31 +def : MipsInstAlias<"exts $rt, $rs, $pos, $lenm1", + (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rs, + uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, + ASE_CNMIPS; +def : MipsInstAlias<"exts $rt, $pos, $lenm1", + (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rt, + uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, + ASE_CNMIPS; + +// cins with $pos 32-63 in converted to cins32 with $pos 0-31 +def : MipsInstAlias<"cins $rt, $rs, $pos, $lenm1", + (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rs, + uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, + ASE_CNMIPS; +def : MipsInstAlias<"cins $rt, $pos, $lenm1", + (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rt, + uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, + ASE_CNMIPS; + //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index 0ad0d344efb..9b4b9d17818 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -372,12 +372,12 @@ class ADDUH_QB_DESC_BASE { + Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> { dag OutOperandList = (outs GPR32Opnd:$rt); - dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$sa, GPR32Opnd:$src); + dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); list Pattern = [(set GPR32Opnd:$rt, - (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, ImmOp:$sa))]; + (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))]; InstrItinClass Itinerary = itin; string Constraints = "$src = $rt"; } @@ -1074,14 +1074,14 @@ class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph, NoItinerary, DSPROpnd>; // Misc -class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5, +class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, immZExt5, NoItinerary>; -class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2, +class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, immZExt2, NoItinerary>; -class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5, - NoItinerary>; +class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5, + immZExt5, NoItinerary>; // Pseudos. def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6]; } +class ASE_CNMIPS { + list InsnPredicates = [HasCnMips]; +} + class ASE_MSA { list InsnPredicates = [HasMSA]; } @@ -390,8 +394,29 @@ class ConstantUImmAsmOperandClass Supers = [], let DiagnosticType = "UImm" # Bits # "_" # Offset; } +def ConstantUImm5Plus32NormalizeAsmOperandClass + : ConstantUImmAsmOperandClass<5, [], 32> { + // We must also subtract 32 when we render the operand. + let RenderMethod = "addConstantUImmOperands<5, 32, -32>"; +} +def ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass { + let Name = "UImm5Lsl2"; + let RenderMethod = "addImmOperands"; + let PredicateMethod = "isScaledUImm<5, 2>"; + let SuperClasses = []; + let DiagnosticType = "UImm5_Lsl2"; +} +def ConstantUImm5ReportUImm6AsmOperandClass + : ConstantUImmAsmOperandClass<5, []> { + let Name = "ConstantUImm5_0_Report_UImm6"; + let DiagnosticType = "UImm5_0_Report_UImm6"; +} +def ConstantUImm5AsmOperandClass + : ConstantUImmAsmOperandClass<5, []>; def ConstantUImm4AsmOperandClass - : ConstantUImmAsmOperandClass<4, []>; + : ConstantUImmAsmOperandClass< + 4, [ConstantUImm5AsmOperandClass, + ConstantUImm5Plus32NormalizeAsmOperandClass]>; def ConstantUImm3AsmOperandClass : ConstantUImmAsmOperandClass<3, [ConstantUImm4AsmOperandClass]>; def ConstantUImm2Plus1AsmOperandClass @@ -453,8 +478,8 @@ def simm18_lsl3 : Operand { let ParserMatchClass = MipsJumpTargetAsmOperand; } -def simm20 : Operand { -} +def simm20 : Operand; +def simm32 : Operand; def uimm20 : Operand { } @@ -481,7 +506,7 @@ def uimmz : Operand { } // Unsigned Operands -foreach I = {1, 2, 3, 4} in +foreach I = {1, 2, 3, 4, 5} in def uimm # I : Operand { let PrintMethod = "printUnsignedImm"; let ParserMatchClass = @@ -495,8 +520,34 @@ def uimm2_plus1 : Operand { let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass; } -def uimm5 : Operand { +def uimm5_plus32_normalize : Operand { + let PrintMethod = "printUnsignedImm"; + let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; +} + +def uimm5_lsl2 : Operand { + let EncoderMethod = "getUImm5Lsl2Encoding"; + let DecoderMethod = "DecodeUImm5lsl2"; + let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass; +} + +def uimm5_plus32_normalize_64 : Operand { + let PrintMethod = "printUnsignedImm"; + let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; +} + +foreach I = {5} in + def uimm # I # _64 : Operand { + let PrintMethod = "printUnsignedImm"; + let ParserMatchClass = + !cast("ConstantUImm" # I # "AsmOperandClass"); + } + +// Like uimm5_64 but reports a less confusing error for 32-63 when +// an instruction alias permits that. +def uimm5_64_report_uimm6 : Operand { let PrintMethod = "printUnsignedImm"; + let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; } def uimm6 : Operand { @@ -1847,7 +1898,7 @@ def : MipsInstAlias<"sync", class LoadImmediate32 : MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), !strconcat(instr_asm, "\t$rt, $imm32")> ; -def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>; +def LoadImm32 : LoadImmediate32<"li", simm32, GPR32Opnd>; class LoadAddressFromReg32 : @@ -1858,7 +1909,7 @@ def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>; class LoadAddressFromImm32 : MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), !strconcat(instr_asm, "\t$rt, $imm32")> ; -def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>; +def LoadAddrImm32 : LoadAddressFromImm32<"la", simm32, GPR32Opnd>; def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), "jal\t$rd, $rs"> ; diff --git a/test/MC/Mips/cnmips/invalid.s b/test/MC/Mips/cnmips/invalid.s new file mode 100644 index 00000000000..52e71102e46 --- /dev/null +++ b/test/MC/Mips/cnmips/invalid.s @@ -0,0 +1,15 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=octeon 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat +foo: + bbit0 $19, -1, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate + bbit0 $19, 64, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate + bbit032 $19, -1, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate + bbit032 $19, 32, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate + bbit1 $19, -1, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate + bbit1 $19, 64, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate + bbit132 $19, -1, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate + bbit132 $19, 32, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/dspr2/invalid.s b/test/MC/Mips/dspr2/invalid.s index 88bade7bacd..16eb8faa112 100644 --- a/test/MC/Mips/dspr2/invalid.s +++ b/test/MC/Mips/dspr2/invalid.s @@ -1,6 +1,17 @@ -# RUN: not llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mattr=dspr2 2>%t1 +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -mattr=+dspr2 -show-encoding 2>%t1 # RUN: FileCheck %s < %t1 - + append $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate + append $2, $3, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate + balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate + balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate + precr_sra.ph.w $24, $25, -1 # CHECK: :[[@LINE]]:28: error: expected 5-bit unsigned immediate + precr_sra.ph.w $24, $25, 32 # CHECK: :[[@LINE]]:28: error: expected 5-bit unsigned immediate + precr_sra_r.ph.w $25 ,$26, -1 # CHECK: :[[@LINE]]:30: error: expected 5-bit unsigned immediate + precr_sra_r.ph.w $25 ,$26, 32 # CHECK: :[[@LINE]]:30: error: expected 5-bit unsigned immediate + prepend $2, $3, -1 # CHECK: :[[@LINE]]:19: error: expected 5-bit unsigned immediate + prepend $2, $3, 32 # CHECK: :[[@LINE]]:19: error: expected 5-bit unsigned immediate shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate diff --git a/test/MC/Mips/dspr2/valid.s b/test/MC/Mips/dspr2/valid.s index 5635402211f..d86081ec464 100644 --- a/test/MC/Mips/dspr2/valid.s +++ b/test/MC/Mips/dspr2/valid.s @@ -43,3 +43,6 @@ mflo $15 # CHECK: mflo $15 # encoding: [0x00,0x00,0x78,0x12] mthi $16 # CHECK: mthi $16 # encoding: [0x02,0x00,0x00,0x11] mtlo $17 # CHECK: mtlo $17 # encoding: [0x02,0x20,0x00,0x13] + append $2, $3, 3 # CHECK: append $2, $3, 3 # encoding: [0x7c,0x62,0x18,0x31] + balign $4, $5, 1 # CHECK: balign $4, $5, 1 # encoding: [0x7c,0xa4,0x0c,0x31] + prepend $6, $7, 4 # CHECK: prepend $6, $7, 4 # encoding: [0x7c,0xe6,0x20,0x71] diff --git a/test/MC/Mips/eva/invalid.s b/test/MC/Mips/eva/invalid.s new file mode 100644 index 00000000000..2ef4eaaab08 --- /dev/null +++ b/test/MC/Mips/eva/invalid.s @@ -0,0 +1,11 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r2 \ +# RUN: -mattr==eva 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate + cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate + prefe -1, 255($7) # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + prefe 32, 255($7) # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/micromips-invalid.s b/test/MC/Mips/micromips-invalid.s index 99e9eb4fa43..ed0ab1bdc23 100644 --- a/test/MC/Mips/micromips-invalid.s +++ b/test/MC/Mips/micromips-invalid.s @@ -65,8 +65,10 @@ sb16 $7, 4($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sh16 $7, 8($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sw16 $7, 4($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - cache 256, 8($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range - pref 256, 8($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + cache -1, 8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + cache 32, 8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + pref -1, 8($5) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate + pref 32, 8($5) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate beqz16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction bnez16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction @@ -78,13 +80,14 @@ break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wait 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - prefx 33, $8($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range - jraddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jraddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jraddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jraddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jraddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jraddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jraddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jraddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jraddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + prefx -1, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + prefx 32, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + jraddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 diff --git a/test/MC/Mips/micromips/invalid.s b/test/MC/Mips/micromips/invalid.s index ae58d16347c..ee5aafc28c9 100644 --- a/test/MC/Mips/micromips/invalid.s +++ b/test/MC/Mips/micromips/invalid.s @@ -1,7 +1,26 @@ # RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1 # RUN: FileCheck %s < %t1 - break16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate - break16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate - sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate - sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate + break16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate + break16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate + cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + jraddiusp -1 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp -4 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 125 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4 + jraddiusp 128 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4 + pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate + rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate + sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate + sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate + sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sll $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sra $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sra $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + srl $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + srl $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/micromips32r6/invalid.s b/test/MC/Mips/micromips32r6/invalid.s index 48c770a85a7..14259eadaea 100644 --- a/test/MC/Mips/micromips32r6/invalid.s +++ b/test/MC/Mips/micromips32r6/invalid.s @@ -18,6 +18,12 @@ bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swe $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swe $5, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction @@ -36,6 +42,8 @@ lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range lw16 $17, 8($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range @@ -64,15 +72,15 @@ wrpgpr $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wsbh $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + jrcaddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand diff --git a/test/MC/Mips/micromips64r6/invalid.s b/test/MC/Mips/micromips64r6/invalid.s index b71434d33b2..51b9f753048 100644 --- a/test/MC/Mips/micromips64r6/invalid.s +++ b/test/MC/Mips/micromips64r6/invalid.s @@ -16,6 +16,12 @@ bnezc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction bnezc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate dalign $4, $2, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate dalign $4, $2, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction @@ -44,6 +50,8 @@ dmodu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction dmodu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction dmodu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range @@ -72,15 +80,16 @@ wrpgpr $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wsbh $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - jrcaddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + jrcaddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 128 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 + jrcaddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand diff --git a/test/MC/Mips/mips32r2/invalid.s b/test/MC/Mips/mips32r2/invalid.s index ebccc43834e..ab8aebd351a 100644 --- a/test/MC/Mips/mips32r2/invalid.s +++ b/test/MC/Mips/mips32r2/invalid.s @@ -2,9 +2,13 @@ # invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text .set noreorder - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/mips32r3/invalid.s b/test/MC/Mips/mips32r3/invalid.s index f67f4c55ecb..9051088fb38 100644 --- a/test/MC/Mips/mips32r3/invalid.s +++ b/test/MC/Mips/mips32r3/invalid.s @@ -2,9 +2,13 @@ # invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r3 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text .set noreorder - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/mips32r5/invalid.s b/test/MC/Mips/mips32r5/invalid.s index fec30e1426c..0d83005d5cc 100644 --- a/test/MC/Mips/mips32r5/invalid.s +++ b/test/MC/Mips/mips32r5/invalid.s @@ -2,9 +2,13 @@ # invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r5 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text .set noreorder - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/mips32r6/invalid.s b/test/MC/Mips/mips32r6/invalid.s index c96d2c6b66f..452cd3a5ee6 100644 --- a/test/MC/Mips/mips32r6/invalid.s +++ b/test/MC/Mips/mips32r6/invalid.s @@ -28,5 +28,11 @@ local_label: bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 - lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 + cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 + lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s index 58fd8c2063c..409d59e5e88 100644 --- a/test/MC/Mips/mips64-alu-instructions.s +++ b/test/MC/Mips/mips64-alu-instructions.s @@ -74,7 +74,7 @@ # CHECK: daddiu $9, $9, -15001 # encoding: [0x67,0xc5,0x29,0x65] # CHECK: daddu $9, $6, $7 # encoding: [0x2d,0x48,0xc7,0x00] # CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00] -# CHECK: drotr32 $9, $6, 52 # encoding: [0x3e,0x4d,0x26,0x00] +# CHECK: drotr32 $9, $6, 20 # encoding: [0x3e,0x4d,0x26,0x00] # CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70] # CHECK: maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70] # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70] @@ -99,7 +99,7 @@ daddiu $9,-15001 daddu $9,$6,$7 drotr $9, $6, 20 - drotr32 $9, $6, 52 + drotr32 $9, $6, 20 madd $6,$7 maddu $6,$7 msub $6,$7 diff --git a/test/MC/Mips/mips64r2/invalid.s b/test/MC/Mips/mips64r2/invalid.s index f53cfff4043..58eb811c946 100644 --- a/test/MC/Mips/mips64r2/invalid.s +++ b/test/MC/Mips/mips64r2/invalid.s @@ -2,9 +2,15 @@ # invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r2 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text .set noreorder - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/mips64r3/invalid.s b/test/MC/Mips/mips64r3/invalid.s index 99cd0803d20..99071211ba4 100644 --- a/test/MC/Mips/mips64r3/invalid.s +++ b/test/MC/Mips/mips64r3/invalid.s @@ -2,9 +2,15 @@ # invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r3 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text .set noreorder - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/mips64r5/invalid.s b/test/MC/Mips/mips64r5/invalid.s index 8319debaa30..3bdea15f523 100644 --- a/test/MC/Mips/mips64r5/invalid.s +++ b/test/MC/Mips/mips64r5/invalid.s @@ -2,9 +2,15 @@ # invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r5 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text .set noreorder - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/mips64r6/invalid.s b/test/MC/Mips/mips64r6/invalid.s index 06c6b2a0dfd..8d68b51c511 100644 --- a/test/MC/Mips/mips64r6/invalid.s +++ b/test/MC/Mips/mips64r6/invalid.s @@ -26,9 +26,17 @@ local_label: bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate dalign $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate dalign $4, $2, $3, 8 # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 + drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/msa/invalid.s b/test/MC/Mips/msa/invalid.s index acecc7ead8f..a57df3182df 100644 --- a/test/MC/Mips/msa/invalid.s +++ b/test/MC/Mips/msa/invalid.s @@ -15,10 +15,14 @@ sat_s.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_s.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_s.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate + sat_s.w $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + sat_s.w $w31, $w31, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate sat_u.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_u.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_u.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_u.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate + sat_u.w $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + sat_u.w $w31, $w31, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate sldi.b $w0, $w29[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate sldi.b $w0, $w29[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate sldi.d $w4, $w12[-1] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate -- 2.34.1