From 930e05eaefb3ac8275973329bd55b05c4ce8e14c Mon Sep 17 00:00:00 2001 From: Pete Cooper Date: Fri, 1 May 2015 18:57:32 +0000 Subject: [PATCH] [ARM] Transfer the internal flag in thumb2 size reduction. Converting from t2LDRs to tLDRr caused the shift argument to drop the internal flag. This would then throw machine verifier errors. Unfortunately i'm having trouble reducing a test case. I'm going to keep trying, but so far its a scary combination of machine sinking, an 'and i1', loads feeding loads, and a bunch of code which shouldn't change IT block formation, but does. Its not useful to commit a test in that state as we have no way of knowing if it even hits this code reliably in future. rdar://problem/20752113 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236333 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Thumb2SizeReduction.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp index e967e537561..40b07bec9ae 100644 --- a/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -470,9 +470,11 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, unsigned OffsetReg = 0; bool OffsetKill = false; + bool OffsetInternal = false; if (HasShift) { OffsetReg = MI->getOperand(2).getReg(); OffsetKill = MI->getOperand(2).isKill(); + OffsetInternal = MI->getOperand(2).isInternalRead(); if (MI->getOperand(3).getImm()) // Thumb1 addressing mode doesn't support shift. @@ -502,7 +504,8 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); if (HasOffReg) - MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); + MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | + getInternalReadRegState(OffsetInternal)); } // Transfer the rest of operands. -- 2.34.1