From 8bbd2ffc7c7832f6964cff89d6a7f439a8840aea Mon Sep 17 00:00:00 2001
From: Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>
Date: Thu, 29 Oct 2015 10:17:16 +0000
Subject: [PATCH] [mips] Check the register class before replacing
 materializations of zero with $zero in microMIPS.

Summary:
The microMIPS register class GPRMM16 does not contain the $zero register.
However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses
of the $dst register:

  [d]addiu, $dst, $zero, 0

with the $zero register, without checking for membership in the register
class of the target machine operand.

Reviewers: dsanders

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D13984

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251622 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/MipsSEISelDAGToDAG.cpp       | 5 +++++
 test/CodeGen/Mips/micromips-zero-mat-uses.ll | 8 ++++++++
 2 files changed, 13 insertions(+)
 create mode 100644 test/CodeGen/Mips/micromips-zero-mat-uses.ll

diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index dff30c78bb5..6f001ea74b3 100644
--- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -115,6 +115,11 @@ bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
       continue;
 
+    // Also, we have to check that the register class of the operand
+    // contains the zero register.
+    if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
+      continue;
+
     MO.setReg(ZeroReg);
   }
 
diff --git a/test/CodeGen/Mips/micromips-zero-mat-uses.ll b/test/CodeGen/Mips/micromips-zero-mat-uses.ll
new file mode 100644
index 00000000000..b38747a2d2c
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-zero-mat-uses.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips,+nooddspreg -O0 < %s | FileCheck %s
+
+; CHECK: addiu    $[[R0:[0-9]+]], $zero, 0
+; CHECK: subu16   $2, $[[R0]], ${{[0-9]+}}
+define i32 @foo() {
+  %1 = sub i32 0, undef
+  ret i32 %1
+}
-- 
2.34.1