From 894bfb2d423e42acacccbe47d04a698c59ef8c9b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 25 Dec 2015 22:10:08 +0000 Subject: [PATCH] [X86] Move getX86SubSuperRegisterOrZero to X86MCTargetDesc.cpp so it can be used by AsmParser library without depending on X86CodeGen library. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256428 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../X86/AsmParser/X86AsmInstrumentation.cpp | 1 - .../X86/MCTargetDesc/X86MCTargetDesc.cpp | 181 +++++++++++++++++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h | 11 ++ lib/Target/X86/X86RegisterInfo.cpp | 183 +----------------- lib/Target/X86/X86RegisterInfo.h | 10 - 5 files changed, 193 insertions(+), 193 deletions(-) diff --git a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp index 2ef86d5320d..09cc53a8e6d 100644 --- a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp +++ b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp @@ -10,7 +10,6 @@ #include "MCTargetDesc/X86BaseInfo.h" #include "X86AsmInstrumentation.h" #include "X86Operand.h" -#include "X86RegisterInfo.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/MCAsmInfo.h" diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index 7a453fea23b..53a6550acdd 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -268,3 +268,184 @@ extern "C" void LLVMInitializeX86TargetMC() { TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, createX86_64AsmBackend); } + +unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, + bool High) { + switch (Size) { + default: return 0; + case 8: + if (High) { + switch (Reg) { + default: return getX86SubSuperRegisterOrZero(Reg, 64); + case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: + return X86::SI; + case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: + return X86::DI; + case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: + return X86::BP; + case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: + return X86::SP; + case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: + return X86::AH; + case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: + return X86::DH; + case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: + return X86::CH; + case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: + return X86::BH; + } + } else { + switch (Reg) { + default: return 0; + case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: + return X86::AL; + case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: + return X86::DL; + case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: + return X86::CL; + case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: + return X86::BL; + case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: + return X86::SIL; + case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: + return X86::DIL; + case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: + return X86::BPL; + case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: + return X86::SPL; + case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: + return X86::R8B; + case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: + return X86::R9B; + case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: + return X86::R10B; + case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: + return X86::R11B; + case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: + return X86::R12B; + case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: + return X86::R13B; + case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: + return X86::R14B; + case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: + return X86::R15B; + } + } + case 16: + switch (Reg) { + default: return 0; + case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: + return X86::AX; + case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: + return X86::DX; + case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: + return X86::CX; + case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: + return X86::BX; + case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: + return X86::SI; + case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: + return X86::DI; + case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: + return X86::BP; + case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: + return X86::SP; + case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: + return X86::R8W; + case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: + return X86::R9W; + case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: + return X86::R10W; + case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: + return X86::R11W; + case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: + return X86::R12W; + case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: + return X86::R13W; + case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: + return X86::R14W; + case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: + return X86::R15W; + } + case 32: + switch (Reg) { + default: return 0; + case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: + return X86::EAX; + case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: + return X86::EDX; + case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: + return X86::ECX; + case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: + return X86::EBX; + case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: + return X86::ESI; + case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: + return X86::EDI; + case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: + return X86::EBP; + case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: + return X86::ESP; + case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: + return X86::R8D; + case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: + return X86::R9D; + case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: + return X86::R10D; + case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: + return X86::R11D; + case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: + return X86::R12D; + case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: + return X86::R13D; + case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: + return X86::R14D; + case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: + return X86::R15D; + } + case 64: + switch (Reg) { + default: return 0; + case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: + return X86::RAX; + case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: + return X86::RDX; + case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: + return X86::RCX; + case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: + return X86::RBX; + case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: + return X86::RSI; + case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: + return X86::RDI; + case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: + return X86::RBP; + case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: + return X86::RSP; + case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: + return X86::R8; + case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: + return X86::R9; + case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: + return X86::R10; + case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: + return X86::R11; + case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: + return X86::R12; + case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: + return X86::R13; + case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: + return X86::R14; + case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: + return X86::R15; + } + } +} + +unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) { + unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High); + assert(Res != 0 && "Unexpected register or VT"); + return Res; +} + + diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h index f8e4e70e53f..2d2836ff07c 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -98,6 +98,17 @@ MCRelocationInfo *createX86_64MachORelocationInfo(MCContext &Ctx); /// Construct X86-64 ELF relocation info. MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx); + +/// Returns the sub or super register of a specific X86 register. +/// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX. +/// Aborts on error. +unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false); + +/// Returns the sub or super register of a specific X86 register. +/// Like getX86SubSuperRegister() but returns 0 on error. +unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, + bool High = false); + } // End llvm namespace diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 1579a1abfc2..58404433e1a 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -628,186 +628,7 @@ X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const { return FrameReg; } -namespace llvm { -unsigned getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, bool High) { - switch (Size) { - default: return 0; - case 8: - if (High) { - switch (Reg) { - default: return getX86SubSuperRegisterOrZero(Reg, 64); - case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: - return X86::SI; - case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: - return X86::DI; - case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: - return X86::BP; - case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: - return X86::SP; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: - return X86::AH; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: - return X86::DH; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: - return X86::CH; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: - return X86::BH; - } - } else { - switch (Reg) { - default: return 0; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: - return X86::AL; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: - return X86::DL; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: - return X86::CL; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: - return X86::BL; - case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: - return X86::SIL; - case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: - return X86::DIL; - case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: - return X86::BPL; - case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: - return X86::SPL; - case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: - return X86::R8B; - case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: - return X86::R9B; - case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: - return X86::R10B; - case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: - return X86::R11B; - case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: - return X86::R12B; - case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: - return X86::R13B; - case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: - return X86::R14B; - case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: - return X86::R15B; - } - } - case 16: - switch (Reg) { - default: return 0; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: - return X86::AX; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: - return X86::DX; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: - return X86::CX; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: - return X86::BX; - case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: - return X86::SI; - case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: - return X86::DI; - case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: - return X86::BP; - case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: - return X86::SP; - case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: - return X86::R8W; - case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: - return X86::R9W; - case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: - return X86::R10W; - case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: - return X86::R11W; - case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: - return X86::R12W; - case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: - return X86::R13W; - case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: - return X86::R14W; - case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: - return X86::R15W; - } - case 32: - switch (Reg) { - default: return 0; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: - return X86::EAX; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: - return X86::EDX; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: - return X86::ECX; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: - return X86::EBX; - case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: - return X86::ESI; - case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: - return X86::EDI; - case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: - return X86::EBP; - case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: - return X86::ESP; - case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: - return X86::R8D; - case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: - return X86::R9D; - case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: - return X86::R10D; - case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: - return X86::R11D; - case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: - return X86::R12D; - case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: - return X86::R13D; - case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: - return X86::R14D; - case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: - return X86::R15D; - } - case 64: - switch (Reg) { - default: return 0; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: - return X86::RAX; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: - return X86::RDX; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: - return X86::RCX; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: - return X86::RBX; - case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: - return X86::RSI; - case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: - return X86::RDI; - case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: - return X86::RBP; - case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: - return X86::RSP; - case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: - return X86::R8; - case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: - return X86::R9; - case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: - return X86::R10; - case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: - return X86::R11; - case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: - return X86::R12; - case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: - return X86::R13; - case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: - return X86::R14; - case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: - return X86::R15; - } - } -} - -unsigned getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) { - unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High); - assert(Res != 0 && "Unexpected register or VT"); - return Res; -} - -unsigned get512BitSuperRegister(unsigned Reg) { +unsigned llvm::get512BitSuperRegister(unsigned Reg) { if (Reg >= X86::XMM0 && Reg <= X86::XMM31) return X86::ZMM0 + (Reg - X86::XMM0); if (Reg >= X86::YMM0 && Reg <= X86::YMM31) @@ -816,5 +637,3 @@ unsigned get512BitSuperRegister(unsigned Reg) { return Reg; llvm_unreachable("Unexpected SIMD register"); } - -} diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index d57eeab262d..f014c8f6ff6 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -135,16 +135,6 @@ public: unsigned getSlotSize() const { return SlotSize; } }; -/// Returns the sub or super register of a specific X86 register. -/// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX. -/// Aborts on error. -unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false); - -/// Returns the sub or super register of a specific X86 register. -/// Like getX86SubSuperRegister() but returns 0 on error. -unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, - bool High = false); - //get512BitRegister - X86 utility - returns 512-bit super register unsigned get512BitSuperRegister(unsigned Reg); -- 2.34.1