From 7e316839810668b4bddb101f31aaa936b5641379 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Tue, 8 Sep 2015 15:02:50 +0000 Subject: [PATCH] [mips][microMIPS] Implement LLE, LUI, LW and LWE instructions Differential Revision: http://reviews.llvm.org/D1179 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247017 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrFormats.td | 42 ++++++++++++++++++++ lib/Target/Mips/MicroMips32r6InstrInfo.td | 41 +++++++++++++++++++ lib/Target/Mips/MipsInstrInfo.td | 2 +- test/MC/Disassembler/Mips/micromips32r6.txt | 8 ++++ test/MC/Mips/micromips32r6/valid.s | 4 ++ 5 files changed, 96 insertions(+), 1 deletion(-) diff --git a/lib/Target/Mips/MicroMips32r6InstrFormats.td b/lib/Target/Mips/MicroMips32r6InstrFormats.td index 5f3e334813f..5c9a29e3287 100644 --- a/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -254,6 +254,48 @@ class POOL32C_STORE_EVA_FM_MMR6 funct> { let Inst{8-0} = offset; } +class LOAD_WORD_EVA_FM_MMR6 funct> { + bits<5> rt; + bits<21> addr; + bits<5> base = addr{20-16}; + bits<9> offset = addr{8-0}; + + bits<32> Inst; + + let Inst{31-26} = 0b011000; + let Inst{25-21} = rt; + let Inst{20-16} = base; + let Inst{15-12} = 0b0110; + let Inst{11-9} = funct; + let Inst{8-0} = offset; +} + +class LOAD_WORD_FM_MMR6 { + bits<5> rt; + bits<21> addr; + bits<5> base = addr{20-16}; + bits<16> offset = addr{15-0}; + + bits<32> Inst; + + let Inst{31-26} = 0b111111; + let Inst{25-21} = rt; + let Inst{20-16} = base; + let Inst{15-0} = offset; +} + +class LOAD_UPPER_IMM_FM_MMR6 { + bits<5> rt; + bits<16> imm16; + + bits<32> Inst; + + let Inst{31-26} = 0b000100; + let Inst{25-21} = rt; + let Inst{20-16} = 0; + let Inst{15-0} = imm16; +} + class CMP_BRANCH_1R_RT_OFF16_FM_MMR6 funct> : MipsR6Inst { bits<5> rt; bits<16> offset; diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index 6a0fd999435..1cdf0de275f 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -104,6 +104,10 @@ class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>; class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>; class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>; class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>; +class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>; +class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>; +class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; +class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6; class CMP_CBR_RT_Z_MMR6_DESC_BASE @@ -637,6 +641,39 @@ class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>; class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>; class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>; +class LOAD_WORD_EVA_MMR6_DESC_BASE : + MMR6Arch, MipsR6Inst { + dag OutOperandList = (outs RO:$rt); + dag InOperandList = (ins mem_mm_12:$addr); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + string DecoderMethod = "DecodeMemMMImm9"; + bit mayLoad = 1; +} +class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>; +class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>; + +class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst { + dag OutOperandList = (outs GPR32Opnd:$rt); + dag InOperandList = (ins mem:$addr); + string AsmString = "lw\t$rt, $addr"; + let DecoderMethod = "DecodeMemMMImm16"; + let canFoldAsLoad = 1; + let mayLoad = 1; + list Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))]; + InstrItinClass Itinerary = II_LW; +} + +class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{ + dag OutOperandList = (outs GPR32Opnd:$rt); + dag InOperandList = (ins uimm16:$imm16); + string AsmString = "lui\t$rt, $imm16"; + list Pattern = []; + bit hasSideEffects = 0; + bit isReMaterializable = 1; + InstrItinClass Itinerary = II_LUI; + Format Form = FrmI; +} + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -825,6 +862,10 @@ def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6; def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6; def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6; def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6; +def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6; +def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6; +def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6; +def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index d2072af71de..a05f7113f16 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1225,7 +1225,7 @@ def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, LW_FM<0x21>; def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; let AdditionalPredicates = [NotInMicroMips] in { -def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, +def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, LW_FM<0x23>; } def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt index a4ef0776c67..cc71c9ccca6 100644 --- a/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/test/MC/Disassembler/Mips/micromips32r6.txt @@ -142,6 +142,14 @@ 0x60 0x85 0xaa 0x06 # CHECK: she $4, 6($5) +0x60 0x85 0x6c 0x06 # CHECK: lle $4, 6($5) + +0x60 0x85 0x6e 0x06 # CHECK: lwe $4, 6($5) + +0xfc 0x85 0x00 0x06 # CHECK: lw $4, 6($5) + +0x10 0xc0 0x45 0x67 # CHECK: lui $6, 17767 + 0x00 0x64 0x2b 0x3c # CHECK: seb $3, $4 0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4 diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index 6d1ee810fa2..5317321185e 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -168,4 +168,8 @@ sce $4, 6($5) # CHECK: sce $4, 6($5) # encoding: [0x60,0x85,0xac,0x06] sh $4, 6($5) # CHECK: sh $4, 6($5) # encoding: [0x38,0x85,0x00,0x06] she $4, 6($5) # CHECK: she $4, 6($5) # encoding: [0x60,0x85,0xaa,0x06] + lle $4, 6($5) # CHECK: lle $4, 6($5) # encoding: [0x60,0x85,0x6c,0x06] + lwe $4, 6($5) # CHECK: lwe $4, 6($5) # encoding: [0x60,0x85,0x6e,0x06] + lw $4, 6($5) # CHECK: lw $4, 6($5) # encoding: [0xfc,0x85,0x00,0x06] + lui $6, 17767 # CHECK: lui $6, 17767 # encoding: [0x10,0xc0,0x45,0x67] -- 2.34.1