From 7e3012c34509a5c1e7c891bcadb5caaed462deb1 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Sat, 17 Jul 2010 06:56:35 +0000 Subject: [PATCH] Another attempt at getting the clang self-host to like my instcombine patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108614 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../InstCombine/InstCombineAndOrXor.cpp | 32 +++++++++++++++++++ test/Transforms/InstCombine/bit-checks.ll | 26 +++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 test/Transforms/InstCombine/bit-checks.ll diff --git a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 3f4a857c41a..35b55428f0c 100644 --- a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -472,6 +472,22 @@ Value *InstCombiner::FoldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS) { Value *NewOr = Builder->CreateOr(Val, Val2); return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } + + // (icmp ne (A & C1), 0) & (icmp ne (A & C2), 0) --> + // (icmp eq (A & (C1|C2)), (C1|C2)) where C1 and C2 are non-zero POT + if (LHSCC == ICmpInst::ICMP_NE && LHSCst->isZero()) { + Value *Op1 = 0, *Op2 = 0; + ConstantInt *CI1 = 0, *CI2 = 0; + if (match(LHS->getOperand(0), m_And(m_Value(Op1), m_ConstantInt(CI1))) && + match(RHS->getOperand(0), m_And(m_Value(Op2), m_ConstantInt(CI2)))) { + if (Op1 == Op2 && !CI1->isZero() && !CI2->isZero() && + CI1->getValue().isPowerOf2() && CI2->getValue().isPowerOf2()) { + Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); + Value *NewAnd = Builder->CreateAnd(Op1, ConstOr); + return Builder->CreateICmp(ICmpInst::ICMP_EQ, NewAnd, ConstOr); + } + } + } } // From here on, we only handle: @@ -1158,6 +1174,22 @@ Value *InstCombiner::FoldOrOfICmps(ICmpInst *LHS, ICmpInst *RHS) { return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } + // (icmp eq (A & C1), 0) | (icmp eq (A & C2), 0) --> + // (icmp ne (A & (C1|C2)), (C1|C2)) where C1 and C2 are non-zero POT + if (LHSCC == ICmpInst::ICMP_EQ && LHSCst->isZero()) { + Value *Op1 = 0, *Op2 = 0; + ConstantInt *CI1 = 0, *CI2 = 0; + if (match(LHS->getOperand(0), m_And(m_Value(Op1), m_ConstantInt(CI1))) && + match(RHS->getOperand(0), m_And(m_Value(Op2), m_ConstantInt(CI2)))) { + if (Op1 == Op2 && !CI1->isZero() && !CI2->isZero() && + CI1->getValue().isPowerOf2() && CI2->getValue().isPowerOf2()) { + Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); + Value *NewAnd = Builder->CreateAnd(Op1, ConstOr); + return Builder->CreateICmp(ICmpInst::ICMP_NE, NewAnd, ConstOr); + } + } + } + // From here on, we only handle: // (icmp1 A, C1) | (icmp2 A, C2) --> something simpler. if (Val != Val2) return 0; diff --git a/test/Transforms/InstCombine/bit-checks.ll b/test/Transforms/InstCombine/bit-checks.ll new file mode 100644 index 00000000000..d774c0972de --- /dev/null +++ b/test/Transforms/InstCombine/bit-checks.ll @@ -0,0 +1,26 @@ +; This test makes sure that these instructions are properly eliminated. +; +; RUN: opt < %s -instcombine -S | \ +; RUN: not grep {tobool} +; END. +define i32 @main(i32 %argc, i8** %argv) nounwind ssp { +entry: + %and = and i32 %argc, 1 ; [#uses=1] + %tobool = icmp ne i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, 2 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 0 ; [#uses=1] + %or.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %retval.0 = select i1 %or.cond, i32 2, i32 1 ; [#uses=1] + ret i32 %retval.0 +} + +define i32 @main2(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 1 ; [#uses=1] + %tobool = icmp eq i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, 2 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 0 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} \ No newline at end of file -- 2.34.1