From 7e18b99f1ed516f7883f806224a730302e4f6e28 Mon Sep 17 00:00:00 2001 From: Manuel Jacob Date: Tue, 18 Mar 2014 16:14:11 +0000 Subject: [PATCH] X86: Use enums for memory operand decoding instead of integer literals. Summary: X86BaseInfo.h defines an enum for the offset of each operand in a memory operand sequence. Some code uses it and some does not. This patch replaces (hopefully) all remaining locations where an integer literal was used instead of this enum. No functionality change intended. Reviewers: nadav CC: llvm-commits, t.p.northover Differential Revision: http://llvm-reviews.chandlerc.com/D3108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204158 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../X86/InstPrinter/X86ATTInstPrinter.cpp | 16 ++++----- .../X86/InstPrinter/X86IntelInstPrinter.cpp | 16 ++++----- lib/Target/X86/X86AsmPrinter.cpp | 36 +++++++++---------- lib/Target/X86/X86InstrInfo.h | 19 +++++----- lib/Target/X86/X86MCInstLower.cpp | 20 +++++------ 5 files changed, 54 insertions(+), 53 deletions(-) diff --git a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp index 4be686aa7a7..eea0a760734 100644 --- a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp @@ -182,16 +182,16 @@ void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O) { - const MCOperand &BaseReg = MI->getOperand(Op); - const MCOperand &IndexReg = MI->getOperand(Op+2); - const MCOperand &DispSpec = MI->getOperand(Op+3); - const MCOperand &SegReg = MI->getOperand(Op+4); + const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); + const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); + const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); + const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); O << markup("getOperand(Op+1).getImm(); + printOperand(MI, Op+X86::AddrIndexReg, O); + unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); if (ScaleVal != 1) { O << ',' << markup("getOperand(Op); - unsigned ScaleVal = MI->getOperand(Op+1).getImm(); - const MCOperand &IndexReg = MI->getOperand(Op+2); - const MCOperand &DispSpec = MI->getOperand(Op+3); - const MCOperand &SegReg = MI->getOperand(Op+4); + const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); + unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); + const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); + const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); + const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); // If this has a segment register, print it. if (SegReg.getReg()) { - printOperand(MI, Op+4, O); + printOperand(MI, Op+X86::AddrSegmentReg, O); O << ':'; } @@ -178,7 +178,7 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, bool NeedPlus = false; if (BaseReg.getReg()) { - printOperand(MI, Op, O); + printOperand(MI, Op+X86::AddrBaseReg, O); NeedPlus = true; } @@ -186,7 +186,7 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, if (NeedPlus) O << " + "; if (ScaleVal != 1) O << ScaleVal << '*'; - printOperand(MI, Op+2, O); + printOperand(MI, Op+X86::AddrIndexReg, O); NeedPlus = true; } diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp index 1a890b6faa4..99d077f1b70 100644 --- a/lib/Target/X86/X86AsmPrinter.cpp +++ b/lib/Target/X86/X86AsmPrinter.cpp @@ -235,9 +235,9 @@ static void printOperand(X86AsmPrinter &P, const MachineInstr *MI, static void printLeaMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = NULL) { - const MachineOperand &BaseReg = MI->getOperand(Op); - const MachineOperand &IndexReg = MI->getOperand(Op+2); - const MachineOperand &DispSpec = MI->getOperand(Op+3); + const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); + const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); + const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); // If we really don't want to print out (rip), don't. bool HasBaseReg = BaseReg.getReg() != 0; @@ -259,7 +259,7 @@ static void printLeaMemReference(X86AsmPrinter &P, const MachineInstr *MI, } case MachineOperand::MO_GlobalAddress: case MachineOperand::MO_ConstantPoolIndex: - printSymbolOperand(P, MI->getOperand(Op + 3), O); + printSymbolOperand(P, DispSpec, O); } if (Modifier && strcmp(Modifier, "H") == 0) @@ -271,12 +271,12 @@ static void printLeaMemReference(X86AsmPrinter &P, const MachineInstr *MI, O << '('; if (HasBaseReg) - printOperand(P, MI, Op, O, Modifier); + printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier); if (IndexReg.getReg()) { O << ','; - printOperand(P, MI, Op+2, O, Modifier); - unsigned ScaleVal = MI->getOperand(Op+1).getImm(); + printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier); + unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); if (ScaleVal != 1) O << ',' << ScaleVal; } @@ -288,9 +288,9 @@ static void printMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = NULL) { assert(isMem(MI, Op) && "Invalid memory reference!"); - const MachineOperand &Segment = MI->getOperand(Op+4); + const MachineOperand &Segment = MI->getOperand(Op+X86::AddrSegmentReg); if (Segment.getReg()) { - printOperand(P, MI, Op+4, O, Modifier); + printOperand(P, MI, Op+X86::AddrSegmentReg, O, Modifier); O << ':'; } printLeaMemReference(P, MI, Op, O, Modifier); @@ -300,15 +300,15 @@ static void printIntelMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = NULL, unsigned AsmVariant = 1) { - const MachineOperand &BaseReg = MI->getOperand(Op); - unsigned ScaleVal = MI->getOperand(Op+1).getImm(); - const MachineOperand &IndexReg = MI->getOperand(Op+2); - const MachineOperand &DispSpec = MI->getOperand(Op+3); - const MachineOperand &SegReg = MI->getOperand(Op+4); + const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); + unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); + const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); + const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); + const MachineOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); // If this has a segment register, print it. if (SegReg.getReg()) { - printOperand(P, MI, Op+4, O, Modifier, AsmVariant); + printOperand(P, MI, Op+X86::AddrSegmentReg, O, Modifier, AsmVariant); O << ':'; } @@ -316,7 +316,7 @@ static void printIntelMemReference(X86AsmPrinter &P, const MachineInstr *MI, bool NeedPlus = false; if (BaseReg.getReg()) { - printOperand(P, MI, Op, O, Modifier, AsmVariant); + printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier, AsmVariant); NeedPlus = true; } @@ -324,13 +324,13 @@ static void printIntelMemReference(X86AsmPrinter &P, const MachineInstr *MI, if (NeedPlus) O << " + "; if (ScaleVal != 1) O << ScaleVal << '*'; - printOperand(P, MI, Op+2, O, Modifier, AsmVariant); + printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier, AsmVariant); NeedPlus = true; } if (!DispSpec.isImm()) { if (NeedPlus) O << " + "; - printOperand(P, MI, Op+3, O, Modifier, AsmVariant); + printOperand(P, MI, Op+X86::AddrDisp, O, Modifier, AsmVariant); } else { int64_t DispVal = DispSpec.getImm(); if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index a02db038f8c..6a6377f7ffb 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -111,19 +111,20 @@ inline static bool isScale(const MachineOperand &MO) { inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { if (MI->getOperand(Op).isFI()) return true; - return Op+4 <= MI->getNumOperands() && - MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && - MI->getOperand(Op+2).isReg() && - (MI->getOperand(Op+3).isImm() || - MI->getOperand(Op+3).isGlobal() || - MI->getOperand(Op+3).isCPI() || - MI->getOperand(Op+3).isJTI()); + return Op+X86::AddrSegmentReg <= MI->getNumOperands() && + MI->getOperand(Op+X86::AddrBaseReg).isReg() && + isScale(MI->getOperand(Op+X86::AddrScaleAmt)) && + MI->getOperand(Op+X86::AddrIndexReg).isReg() && + (MI->getOperand(Op+X86::AddrDisp).isImm() || + MI->getOperand(Op+X86::AddrDisp).isGlobal() || + MI->getOperand(Op+X86::AddrDisp).isCPI() || + MI->getOperand(Op+X86::AddrDisp).isJTI()); } inline static bool isMem(const MachineInstr *MI, unsigned Op) { if (MI->getOperand(Op).isFI()) return true; - return Op+5 <= MI->getNumOperands() && - MI->getOperand(Op+4).isReg() && + return Op+X86::AddrNumOperands <= MI->getNumOperands() && + MI->getOperand(Op+X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op); } diff --git a/lib/Target/X86/X86MCInstLower.cpp b/lib/Target/X86/X86MCInstLower.cpp index 3dabbd72ede..b365802cbe9 100644 --- a/lib/Target/X86/X86MCInstLower.cpp +++ b/lib/Target/X86/X86MCInstLower.cpp @@ -296,12 +296,12 @@ static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned RegOp = IsStore ? 0 : 5; unsigned AddrOp = AddrBase + 3; assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && - Inst.getOperand(AddrBase + 0).isReg() && // base - Inst.getOperand(AddrBase + 1).isImm() && // scale - Inst.getOperand(AddrBase + 2).isReg() && // index register - (Inst.getOperand(AddrOp).isExpr() || // address - Inst.getOperand(AddrOp).isImm())&& - Inst.getOperand(AddrBase + 4).isReg() && // segment + Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && + Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && + Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && + Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && + (Inst.getOperand(AddrOp).isExpr() || + Inst.getOperand(AddrOp).isImm()) && "Unexpected instruction!"); // Check whether the destination register can be fixed. @@ -321,14 +321,14 @@ static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, } if (Absolute && - (Inst.getOperand(AddrBase + 0).getReg() != 0 || - Inst.getOperand(AddrBase + 2).getReg() != 0 || - Inst.getOperand(AddrBase + 1).getImm() != 1)) + (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || + Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || + Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) return; // If so, rewrite the instruction. MCOperand Saved = Inst.getOperand(AddrOp); - MCOperand Seg = Inst.getOperand(AddrBase + 4); + MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); Inst = MCInst(); Inst.setOpcode(Opcode); Inst.addOperand(Saved); -- 2.34.1