From 6e50c921d037b032e22999ab0694ba4676d4b812 Mon Sep 17 00:00:00 2001 From: Alex Lorenz Date: Tue, 14 Jul 2015 21:24:41 +0000 Subject: [PATCH] MIR Serialization: Serialize the machine basic block live in registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242204 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MIRYamlMapping.h | 5 ++-- lib/CodeGen/MIRParser/MIParser.cpp | 21 ++++++++++++++++ lib/CodeGen/MIRParser/MIParser.h | 6 +++++ lib/CodeGen/MIRParser/MIRParser.cpp | 8 ++++++ lib/CodeGen/MIRPrinter.cpp | 10 +++++++- test/CodeGen/MIR/X86/basic-block-liveins.mir | 25 +++++++++++++++++++ .../X86/expected-named-register-livein.mir | 21 ++++++++++++++++ 7 files changed, 93 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/MIR/X86/basic-block-liveins.mir create mode 100644 test/CodeGen/MIR/X86/expected-named-register-livein.mir diff --git a/include/llvm/CodeGen/MIRYamlMapping.h b/include/llvm/CodeGen/MIRYamlMapping.h index 2ecd445f0de..9798e5cef64 100644 --- a/include/llvm/CodeGen/MIRYamlMapping.h +++ b/include/llvm/CodeGen/MIRYamlMapping.h @@ -102,9 +102,9 @@ struct MachineBasicBlock { unsigned Alignment = 0; bool IsLandingPad = false; bool AddressTaken = false; - // TODO: Serialize the successor weights and liveins. + // TODO: Serialize the successor weights. std::vector Successors; - + std::vector LiveIns; std::vector Instructions; }; @@ -117,6 +117,7 @@ template <> struct MappingTraits { YamlIO.mapOptional("isLandingPad", MBB.IsLandingPad); YamlIO.mapOptional("addressTaken", MBB.AddressTaken); YamlIO.mapOptional("successors", MBB.Successors); + YamlIO.mapOptional("liveins", MBB.LiveIns); YamlIO.mapOptional("instructions", MBB.Instructions); } }; diff --git a/lib/CodeGen/MIRParser/MIParser.cpp b/lib/CodeGen/MIRParser/MIParser.cpp index dec06bc9cc8..c00011288a6 100644 --- a/lib/CodeGen/MIRParser/MIParser.cpp +++ b/lib/CodeGen/MIRParser/MIParser.cpp @@ -78,6 +78,7 @@ public: bool parse(MachineInstr *&MI); bool parseMBB(MachineBasicBlock *&MBB); + bool parseNamedRegister(unsigned &Reg); bool parseRegister(unsigned &Reg); bool parseRegisterFlag(unsigned &Flags); @@ -215,6 +216,18 @@ bool MIParser::parseMBB(MachineBasicBlock *&MBB) { return false; } +bool MIParser::parseNamedRegister(unsigned &Reg) { + lex(); + if (Token.isNot(MIToken::NamedRegister)) + return error("expected a named register"); + if (parseRegister(Reg)) + return 0; + lex(); + if (Token.isNot(MIToken::Eof)) + return error("expected end of string after the register reference"); + return false; +} + static const char *printImplicitRegisterFlag(const MachineOperand &MO) { assert(MO.isImplicit()); return MO.isDef() ? "implicit-def" : "implicit"; @@ -583,3 +596,11 @@ bool llvm::parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM, const SlotMapping &IRSlots, SMDiagnostic &Error) { return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseMBB(MBB); } + +bool llvm::parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM, + MachineFunction &MF, StringRef Src, + const PerFunctionMIParsingState &PFS, + const SlotMapping &IRSlots, + SMDiagnostic &Error) { + return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseNamedRegister(Reg); +} diff --git a/lib/CodeGen/MIRParser/MIParser.h b/lib/CodeGen/MIRParser/MIParser.h index 8a911b32a76..fca4c4e6f88 100644 --- a/lib/CodeGen/MIRParser/MIParser.h +++ b/lib/CodeGen/MIRParser/MIParser.h @@ -40,6 +40,12 @@ bool parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM, const PerFunctionMIParsingState &PFS, const SlotMapping &IRSlots, SMDiagnostic &Error); +bool parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM, + MachineFunction &MF, StringRef Src, + const PerFunctionMIParsingState &PFS, + const SlotMapping &IRSlots, + SMDiagnostic &Error); + } // end namespace llvm #endif diff --git a/lib/CodeGen/MIRParser/MIRParser.cpp b/lib/CodeGen/MIRParser/MIRParser.cpp index bfec6c59164..16b0e165589 100644 --- a/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/lib/CodeGen/MIRParser/MIRParser.cpp @@ -321,6 +321,14 @@ bool MIRParserImpl::initializeMachineBasicBlock( // TODO: Report an error when adding the same successor more than once. MBB.addSuccessor(SuccMBB); } + // Parse the liveins. + for (const auto &LiveInSource : YamlMBB.LiveIns) { + unsigned Reg = 0; + if (parseNamedRegisterReference(Reg, SM, MF, LiveInSource.Value, PFS, + IRSlots, Error)) + return error(Error, LiveInSource.SourceRange); + MBB.addLiveIn(Reg); + } // Parse the instructions. for (const auto &MISource : YamlMBB.Instructions) { MachineInstr *MI = nullptr; diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp index ddc1d0a0cc1..d5cf9244199 100644 --- a/lib/CodeGen/MIRPrinter.cpp +++ b/lib/CodeGen/MIRPrinter.cpp @@ -233,7 +233,15 @@ void MIRPrinter::convert(ModuleSlotTracker &MST, MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB); YamlMBB.Successors.push_back(StrOS.str()); } - + // Print the live in registers. + const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo(); + assert(TRI && "Expected target register info"); + for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) { + std::string Str; + raw_string_ostream StrOS(Str); + printReg(*I, StrOS, TRI); + YamlMBB.LiveIns.push_back(StrOS.str()); + } // Print the machine instructions. YamlMBB.Instructions.reserve(MBB.size()); std::string Str; diff --git a/test/CodeGen/MIR/X86/basic-block-liveins.mir b/test/CodeGen/MIR/X86/basic-block-liveins.mir new file mode 100644 index 00000000000..d749a052442 --- /dev/null +++ b/test/CodeGen/MIR/X86/basic-block-liveins.mir @@ -0,0 +1,25 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses basic block liveins correctly. + +--- | + + define i32 @test(i32 %a, i32 %b) { + body: + %c = add i32 %a, %b + ret i32 %c + } + +... +--- +name: test +body: + # CHECK: name: body + # CHECK: liveins: [ '%edi', '%esi' ] + # CHECK-NEXT: instructions: + - id: 0 + name: body + liveins: [ '%edi', '%esi' ] + instructions: + - '%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _' + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/expected-named-register-livein.mir b/test/CodeGen/MIR/X86/expected-named-register-livein.mir new file mode 100644 index 00000000000..1fbe881c8c7 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-named-register-livein.mir @@ -0,0 +1,21 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %a) { + body: + ret i32 %a + } + +... +--- +name: test +body: + - id: 0 + name: body + # CHECK: [[@LINE+1]]:21: expected a named register + liveins: [ '%0' ] + instructions: + - '%eax = COPY %edi' + - 'RETQ %eax' +... -- 2.34.1