From 659e09e3729b903ee299300e4d29a482ce986bab Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Fri, 4 Apr 2014 14:49:30 +0000 Subject: [PATCH] DAGLegalize: add last-ditch type-legalization for VSELECT. When LLVM sees something like (v1iN (vselect v1i1, v1iN, v1iN)) it can decide that the result is OK (v1i64 is legal on AArch64, for example) but it still need scalarising because of that v1i1. There was no code to do this though. AArch64 and ARM64 have DAG combines to produce efficient code and prevent that occuring in *most* such situations, but there are edge cases that they miss. This adds a legalization to cope with that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205626 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 + lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 15 +++++++++++++++ test/CodeGen/ARM64/neon-v1i1-setcc.ll | 9 +++++++++ 3 files changed, 25 insertions(+) diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 947ea10fd70..835d34f004f 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -540,6 +540,7 @@ private: SDValue ScalarizeVecOp_UnaryOp(SDNode *N); SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N); SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N); + SDValue ScalarizeVecOp_VSELECT(SDNode *N); SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo); SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo); diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 04de324eabf..3c7f111a33e 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -394,6 +394,9 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { case ISD::EXTRACT_VECTOR_ELT: Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break; + case ISD::VSELECT: + Res = ScalarizeVecOp_VSELECT(N); + break; case ISD::STORE: Res = ScalarizeVecOp_STORE(cast(N), OpNo); break; @@ -462,6 +465,18 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { return Res; } + +/// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be +/// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT +/// (still with vector output type since that was acceptable if we got here). +SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) { + SDValue ScalarCond = GetScalarizedVector(N->getOperand(0)); + EVT VT = N->getValueType(0); + + return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1), + N->getOperand(2)); +} + /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be /// scalarized, it must be <1 x ty>. Just store the element. SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ diff --git a/test/CodeGen/ARM64/neon-v1i1-setcc.ll b/test/CodeGen/ARM64/neon-v1i1-setcc.ll index a7e59fbc002..d7a0771f7b1 100644 --- a/test/CodeGen/ARM64/neon-v1i1-setcc.ll +++ b/test/CodeGen/ARM64/neon-v1i1-setcc.ll @@ -50,6 +50,15 @@ define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x doubl ret <1 x double> %res } +define <1 x i64> @test_select_v1i1_3(i64 %lhs, i64 %rhs, <1 x i64> %v3) { +; CHECK-LABEL: test_select_v1i1_3: +; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}} + %tst = icmp eq i64 %lhs, %rhs + %evil = insertelement <1 x i1> undef, i1 %tst, i32 0 + %res = select <1 x i1> %evil, <1 x i64> zeroinitializer, <1 x i64> %v3 + ret <1 x i64> %res +} + define i32 @test_br_extr_cmp(<1 x i64> %v1, <1 x i64> %v2) { ; CHECK-LABEL: test_br_extr_cmp: ; CHECK: cmp x{{[0-9]+}}, x{{[0-9]+}} -- 2.34.1