From 648a027c82f27afca8f561afcc9f68298610b364 Mon Sep 17 00:00:00 2001 From: Asaf Badouh Date: Mon, 21 Sep 2015 10:23:53 +0000 Subject: [PATCH] [X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FP Differential Revision: http://reviews.llvm.org/D12524 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248147 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 9 +- lib/Target/X86/X86InstrAVX512.td | 68 ++++------- lib/Target/X86/X86InstrFragmentsSIMD.td | 2 + lib/Target/X86/X86IntrinsicsInfo.h | 6 +- test/MC/X86/avx512-encodings.s | 143 ++++++++++++++++++++++++ 5 files changed, 182 insertions(+), 46 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 4d9bd085658..903879db2c8 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -15890,6 +15890,14 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src), Mask, PassThru, Subtarget, DAG); } + case INTR_TYPE_SCALAR_MASK: { + SDValue Src1 = Op.getOperand(1); + SDValue Src2 = Op.getOperand(2); + SDValue passThru = Op.getOperand(3); + SDValue Mask = Op.getOperand(4); + return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2), + Mask, passThru, Subtarget, DAG); + } case INTR_TYPE_SCALAR_MASK_RM: { SDValue Src1 = Op.getOperand(1); SDValue Src2 = Op.getOperand(2); @@ -16059,7 +16067,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget } case FPCLASS: { // FPclass intrinsics with mask - // SDValue Src1 = Op.getOperand(1); EVT VT = Src1.getValueType(); EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 29e18dd931f..84d8a2bbc80 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -5360,50 +5360,31 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in { } /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd -multiclass avx512_fp14_s opc, string OpcodeStr, RegisterClass RC, - X86MemOperand x86memop> { - let hasSideEffects = 0 in { - def rr : AVX5128I, EVEX_4V; +multiclass avx512_fp14_s opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _> { + let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in { + defm rr : AVX512_maskable_scalar, EVEX_4V; let mayLoad = 1 in { - def rm : AVX5128I, EVEX_4V; + defm rm : AVX512_maskable_scalar, EVEX_4V; } } } -defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>, - EVEX_CD8<32, CD8VT1>; -defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>, - VEX_W, EVEX_CD8<64, CD8VT1>; -defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>, - EVEX_CD8<32, CD8VT1>; -defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>, - VEX_W, EVEX_CD8<64, CD8VT1>; - -def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1), - (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))), - (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X), - (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>; - -def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1), - (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))), - (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X), - (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>; - -def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1), - (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))), - (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X), - (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>; - -def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1), - (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))), - (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X), - (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>; +defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>, + EVEX_CD8<32, CD8VT1>, T8PD; +defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>, + VEX_W, EVEX_CD8<64, CD8VT1>, T8PD; +defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>, + EVEX_CD8<32, CD8VT1>, T8PD; +defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>, + VEX_W, EVEX_CD8<64, CD8VT1>, T8PD; /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd multiclass avx512_fp14_p opc, string OpcodeStr, SDNode OpNode, @@ -5685,15 +5666,14 @@ defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG; let Predicates = [HasAVX512] in { def : Pat<(f32 (X86frsqrt FR32X:$src)), - (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>; + (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>; def : Pat<(f32 (X86frsqrt (load addr:$src))), - (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>, + (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>, Requires<[OptForSize]>; - def : Pat<(f32 (X86frcp FR32X:$src)), - (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>; + (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>; def : Pat<(f32 (X86frcp (load addr:$src))), - (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>, + (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>, Requires<[OptForSize]>; } diff --git a/lib/Target/X86/X86InstrFragmentsSIMD.td b/lib/Target/X86/X86InstrFragmentsSIMD.td index b725a67e2c4..c042e550f4e 100644 --- a/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -58,6 +58,8 @@ def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp, [SDNPCommutative, SDNPAssociative]>; def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; +def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>; +def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>; def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; diff --git a/lib/Target/X86/X86IntrinsicsInfo.h b/lib/Target/X86/X86IntrinsicsInfo.h index c1e35d61da7..5fdb253dd64 100644 --- a/lib/Target/X86/X86IntrinsicsInfo.h +++ b/lib/Target/X86/X86IntrinsicsInfo.h @@ -25,7 +25,7 @@ enum IntrinsicType { INTR_TYPE_2OP_MASK, INTR_TYPE_2OP_MASK_RM, INTR_TYPE_3OP_MASK, INTR_TYPE_3OP_MASK_RM, INTR_TYPE_3OP_IMM8_MASK, FMA_OP_MASK, FMA_OP_MASKZ, FMA_OP_MASK3, VPERM_3OP_MASK, - VPERM_3OP_MASKZ, + VPERM_3OP_MASKZ, INTR_TYPE_SCALAR_MASK, INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK_RM, COMPRESS_EXPAND_IN_REG, COMPRESS_TO_MEM, TRUNCATE_TO_MEM_VI8, TRUNCATE_TO_MEM_VI16, TRUNCATE_TO_MEM_VI32, @@ -1517,10 +1517,14 @@ static const IntrinsicData IntrinsicsWithoutChain[] = { X86_INTRINSIC_DATA(avx512_psad_bw_512, INTR_TYPE_2OP, X86ISD::PSADBW, 0), X86_INTRINSIC_DATA(avx512_psll_dq_512, INTR_TYPE_2OP_IMM8, X86ISD::VSHLDQ, 0), X86_INTRINSIC_DATA(avx512_psrl_dq_512, INTR_TYPE_2OP_IMM8, X86ISD::VSRLDQ, 0), + X86_INTRINSIC_DATA(avx512_rcp14_sd, INTR_TYPE_SCALAR_MASK, X86ISD::FRCP, 0), + X86_INTRINSIC_DATA(avx512_rcp14_ss, INTR_TYPE_SCALAR_MASK, X86ISD::FRCP, 0), X86_INTRINSIC_DATA(avx512_rcp28_pd, INTR_TYPE_1OP_MASK_RM,X86ISD::RCP28, 0), X86_INTRINSIC_DATA(avx512_rcp28_ps, INTR_TYPE_1OP_MASK_RM,X86ISD::RCP28, 0), X86_INTRINSIC_DATA(avx512_rcp28_sd, INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28, 0), X86_INTRINSIC_DATA(avx512_rcp28_ss, INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28, 0), + X86_INTRINSIC_DATA(avx512_rsqrt14_sd, INTR_TYPE_SCALAR_MASK, X86ISD::FRSQRT, 0), + X86_INTRINSIC_DATA(avx512_rsqrt14_ss, INTR_TYPE_SCALAR_MASK, X86ISD::FRSQRT, 0), X86_INTRINSIC_DATA(avx512_rsqrt28_pd, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0), X86_INTRINSIC_DATA(avx512_rsqrt28_ps, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0), X86_INTRINSIC_DATA(avx512_rsqrt28_sd, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RSQRT28, 0), diff --git a/test/MC/X86/avx512-encodings.s b/test/MC/X86/avx512-encodings.s index 1bfa9398d6c..4f0318b55ea 100644 --- a/test/MC/X86/avx512-encodings.s +++ b/test/MC/X86/avx512-encodings.s @@ -17237,3 +17237,146 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2 // CHECK: vcvttss2usi -516(%rdx), %r8 // CHECK: encoding: [0x62,0x71,0xfe,0x08,0x78,0x82,0xfc,0xfd,0xff,0xff] vcvttss2usi -516(%rdx), %r8 +// CHECK: vrsqrt14sd %xmm10, %xmm6, %xmm26 +// CHECK: encoding: [0x62,0x42,0xcd,0x08,0x4f,0xd2] + vrsqrt14sd %xmm10, %xmm6, %xmm26 + +// CHECK: vrsqrt14sd %xmm10, %xmm6, %xmm26 {%k5} +// CHECK: encoding: [0x62,0x42,0xcd,0x0d,0x4f,0xd2] + vrsqrt14sd %xmm10, %xmm6, %xmm26 {%k5} + +// CHECK: vrsqrt14sd %xmm10, %xmm6, %xmm26 {%k5} {z} +// CHECK: encoding: [0x62,0x42,0xcd,0x8d,0x4f,0xd2] + vrsqrt14sd %xmm10, %xmm6, %xmm26 {%k5} {z} + +// CHECK: vrsqrt14sd (%rcx), %xmm6, %xmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x08,0x4f,0x11] + vrsqrt14sd (%rcx), %xmm6, %xmm26 + +// CHECK: vrsqrt14sd 291(%rax,%r14,8), %xmm6, %xmm26 +// CHECK: encoding: [0x62,0x22,0xcd,0x08,0x4f,0x94,0xf0,0x23,0x01,0x00,0x00] + vrsqrt14sd 291(%rax,%r14,8), %xmm6, %xmm26 + +// CHECK: vrsqrt14sd 1016(%rdx), %xmm6, %xmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x08,0x4f,0x52,0x7f] + vrsqrt14sd 1016(%rdx), %xmm6, %xmm26 + +// CHECK: vrsqrt14sd 1024(%rdx), %xmm6, %xmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x08,0x4f,0x92,0x00,0x04,0x00,0x00] + vrsqrt14sd 1024(%rdx), %xmm6, %xmm26 + +// CHECK: vrsqrt14sd -1024(%rdx), %xmm6, %xmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x08,0x4f,0x52,0x80] + vrsqrt14sd -1024(%rdx), %xmm6, %xmm26 + +// CHECK: vrsqrt14sd -1032(%rdx), %xmm6, %xmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x08,0x4f,0x92,0xf8,0xfb,0xff,0xff] + vrsqrt14sd -1032(%rdx), %xmm6, %xmm26 + +// CHECK: vrsqrt14ss %xmm9, %xmm14, %xmm14 +// CHECK: encoding: [0x62,0x52,0x0d,0x08,0x4f,0xf1] + vrsqrt14ss %xmm9, %xmm14, %xmm14 + +// CHECK: vrsqrt14ss %xmm9, %xmm14, %xmm14 {%k1} +// CHECK: encoding: [0x62,0x52,0x0d,0x09,0x4f,0xf1] + vrsqrt14ss %xmm9, %xmm14, %xmm14 {%k1} + +// CHECK: vrsqrt14ss %xmm9, %xmm14, %xmm14 {%k1} {z} +// CHECK: encoding: [0x62,0x52,0x0d,0x89,0x4f,0xf1] + vrsqrt14ss %xmm9, %xmm14, %xmm14 {%k1} {z} + +// CHECK: vrsqrt14ss (%rcx), %xmm14, %xmm14 +// CHECK: encoding: [0x62,0x72,0x0d,0x08,0x4f,0x31] + vrsqrt14ss (%rcx), %xmm14, %xmm14 + +// CHECK: vrsqrt14ss 291(%rax,%r14,8), %xmm14, %xmm14 +// CHECK: encoding: [0x62,0x32,0x0d,0x08,0x4f,0xb4,0xf0,0x23,0x01,0x00,0x00] + vrsqrt14ss 291(%rax,%r14,8), %xmm14, %xmm14 + +// CHECK: vrsqrt14ss 508(%rdx), %xmm14, %xmm14 +// CHECK: encoding: [0x62,0x72,0x0d,0x08,0x4f,0x72,0x7f] + vrsqrt14ss 508(%rdx), %xmm14, %xmm14 + +// CHECK: vrsqrt14ss 512(%rdx), %xmm14, %xmm14 +// CHECK: encoding: [0x62,0x72,0x0d,0x08,0x4f,0xb2,0x00,0x02,0x00,0x00] + vrsqrt14ss 512(%rdx), %xmm14, %xmm14 + +// CHECK: vrsqrt14ss -512(%rdx), %xmm14, %xmm14 +// CHECK: encoding: [0x62,0x72,0x0d,0x08,0x4f,0x72,0x80] + vrsqrt14ss -512(%rdx), %xmm14, %xmm14 + +// CHECK: vrsqrt14ss -516(%rdx), %xmm14, %xmm14 +// CHECK: encoding: [0x62,0x72,0x0d,0x08,0x4f,0xb2,0xfc,0xfd,0xff,0xff] + vrsqrt14ss -516(%rdx), %xmm14, %xmm14 + +// CHECK: vrcp14sd %xmm14, %xmm22, %xmm12 +// CHECK: encoding: [0x62,0x52,0xcd,0x00,0x4d,0xe6] + vrcp14sd %xmm14, %xmm22, %xmm12 + +// CHECK: vrcp14sd %xmm14, %xmm22, %xmm12 {%k2} +// CHECK: encoding: [0x62,0x52,0xcd,0x02,0x4d,0xe6] + vrcp14sd %xmm14, %xmm22, %xmm12 {%k2} + +// CHECK: vrcp14sd %xmm14, %xmm22, %xmm12 {%k2} {z} +// CHECK: encoding: [0x62,0x52,0xcd,0x82,0x4d,0xe6] + vrcp14sd %xmm14, %xmm22, %xmm12 {%k2} {z} + +// CHECK: vrcp14sd (%rcx), %xmm22, %xmm12 +// CHECK: encoding: [0x62,0x72,0xcd,0x00,0x4d,0x21] + vrcp14sd (%rcx), %xmm22, %xmm12 + +// CHECK: vrcp14sd 291(%rax,%r14,8), %xmm22, %xmm12 +// CHECK: encoding: [0x62,0x32,0xcd,0x00,0x4d,0xa4,0xf0,0x23,0x01,0x00,0x00] + vrcp14sd 291(%rax,%r14,8), %xmm22, %xmm12 + +// CHECK: vrcp14sd 1016(%rdx), %xmm22, %xmm12 +// CHECK: encoding: [0x62,0x72,0xcd,0x00,0x4d,0x62,0x7f] + vrcp14sd 1016(%rdx), %xmm22, %xmm12 + +// CHECK: vrcp14sd 1024(%rdx), %xmm22, %xmm12 +// CHECK: encoding: [0x62,0x72,0xcd,0x00,0x4d,0xa2,0x00,0x04,0x00,0x00] + vrcp14sd 1024(%rdx), %xmm22, %xmm12 + +// CHECK: vrcp14sd -1024(%rdx), %xmm22, %xmm12 +// CHECK: encoding: [0x62,0x72,0xcd,0x00,0x4d,0x62,0x80] + vrcp14sd -1024(%rdx), %xmm22, %xmm12 + +// CHECK: vrcp14sd -1032(%rdx), %xmm22, %xmm12 +// CHECK: encoding: [0x62,0x72,0xcd,0x00,0x4d,0xa2,0xf8,0xfb,0xff,0xff] + vrcp14sd -1032(%rdx), %xmm22, %xmm12 + +// CHECK: vrcp14ss %xmm3, %xmm8, %xmm8 +// CHECK: encoding: [0x62,0x72,0x3d,0x08,0x4d,0xc3] + vrcp14ss %xmm3, %xmm8, %xmm8 + +// CHECK: vrcp14ss %xmm3, %xmm8, %xmm8 {%k7} +// CHECK: encoding: [0x62,0x72,0x3d,0x0f,0x4d,0xc3] + vrcp14ss %xmm3, %xmm8, %xmm8 {%k7} + +// CHECK: vrcp14ss %xmm3, %xmm8, %xmm8 {%k7} {z} +// CHECK: encoding: [0x62,0x72,0x3d,0x8f,0x4d,0xc3] + vrcp14ss %xmm3, %xmm8, %xmm8 {%k7} {z} + +// CHECK: vrcp14ss (%rcx), %xmm8, %xmm8 +// CHECK: encoding: [0x62,0x72,0x3d,0x08,0x4d,0x01] + vrcp14ss (%rcx), %xmm8, %xmm8 + +// CHECK: vrcp14ss 291(%rax,%r14,8), %xmm8, %xmm8 +// CHECK: encoding: [0x62,0x32,0x3d,0x08,0x4d,0x84,0xf0,0x23,0x01,0x00,0x00] + vrcp14ss 291(%rax,%r14,8), %xmm8, %xmm8 + +// CHECK: vrcp14ss 508(%rdx), %xmm8, %xmm8 +// CHECK: encoding: [0x62,0x72,0x3d,0x08,0x4d,0x42,0x7f] + vrcp14ss 508(%rdx), %xmm8, %xmm8 + +// CHECK: vrcp14ss 512(%rdx), %xmm8, %xmm8 +// CHECK: encoding: [0x62,0x72,0x3d,0x08,0x4d,0x82,0x00,0x02,0x00,0x00] + vrcp14ss 512(%rdx), %xmm8, %xmm8 + +// CHECK: vrcp14ss -512(%rdx), %xmm8, %xmm8 +// CHECK: encoding: [0x62,0x72,0x3d,0x08,0x4d,0x42,0x80] + vrcp14ss -512(%rdx), %xmm8, %xmm8 + +// CHECK: vrcp14ss -516(%rdx), %xmm8, %xmm8 +// CHECK: encoding: [0x62,0x72,0x3d,0x08,0x4d,0x82,0xfc,0xfd,0xff,0xff] + vrcp14ss -516(%rdx), %xmm8, %xmm8 -- 2.34.1