From 5fa397629b43cf1428395698efdf913042a04ab7 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 5 Dec 2015 17:34:07 +0000 Subject: [PATCH] [Hexagon] Don't call getNumImplicitDefs and then iterate over the count. getNumImplicitDefs contains a loop so its better to just loop over the null terminated implicit def list. NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254852 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Hexagon/MCTargetDesc/HexagonMCChecker.cpp | 49 ++++++++++--------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp index fefe7543f39..46b7b41fec3 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp @@ -85,32 +85,33 @@ void HexagonMCChecker::init(MCInst const& MCI) { } // Get implicit register definitions. - const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); - for (unsigned i = 0; i < MCID.getNumImplicitDefs(); ++i) { - unsigned R = ImpDefs[i]; + if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) + for (; *ImpDef; ++ImpDef) { + unsigned R = *ImpDef; - if (Hexagon::R31 != R && MCID.isCall()) - // Any register other than the LR and the PC are actually volatile ones - // as defined by the ABI, not modified implicitly by the call insn. - continue; - if (Hexagon::PC == R) - // Branches are the only insns that can change the PC, - // otherwise a read-only register. - continue; + if (Hexagon::R31 != R && MCID.isCall()) + // Any register other than the LR and the PC are actually volatile ones + // as defined by the ABI, not modified implicitly by the call insn. + continue; + if (Hexagon::PC == R) + // Branches are the only insns that can change the PC, + // otherwise a read-only register. + continue; - if (Hexagon::USR_OVF == R) - // Many insns change the USR implicitly, but only one or another flag. - // The instruction table models the USR.OVF flag, which can be implicitly - // modified more than once, but cannot be modified in the same packet - // with an instruction that modifies is explicitly. Deal with such situ- - // ations individually. - SoftDefs.insert(R); - else if (isPredicateRegister(R) && HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) - // Include implicit late predicates. - LatePreds.insert(R); - else - Defs[R].insert(PredSense(PredReg, isTrue)); - } + if (Hexagon::USR_OVF == R) + // Many insns change the USR implicitly, but only one or another flag. + // The instruction table models the USR.OVF flag, which can be implicitly + // modified more than once, but cannot be modified in the same packet + // with an instruction that modifies is explicitly. Deal with such situ- + // ations individually. + SoftDefs.insert(R); + else if (isPredicateRegister(R) && + HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) + // Include implicit late predicates. + LatePreds.insert(R); + else + Defs[R].insert(PredSense(PredReg, isTrue)); + } // Figure out explicit register definitions. for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { -- 2.34.1