From 5b870aff81da0c07413f0241087bb3722954b83d Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Tue, 2 Mar 2010 02:14:38 +0000 Subject: [PATCH] Fix several places to handle vector operands properly. Based on a patch by Micah Villmow for PR6438. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97538 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 +++--- .../SelectionDAG/LegalizeIntegerTypes.cpp | 4 ++-- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +- test/CodeGen/X86/vec_cast.ll | 18 +++++++++++++----- 4 files changed, 19 insertions(+), 11 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 0447e3b828e..8ba06698942 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1064,7 +1064,7 @@ SDValue DAGCombiner::visitADD(SDNode *N) { if (VT.isInteger() && !VT.isVector()) { APInt LHSZero, LHSOne; APInt RHSZero, RHSOne; - APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); + APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); if (LHSZero.getBoolValue()) { @@ -1136,7 +1136,7 @@ SDValue DAGCombiner::visitADDC(SDNode *N) { // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. APInt LHSZero, LHSOne; APInt RHSZero, RHSOne; - APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); + APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); if (LHSZero.getBoolValue()) { @@ -2754,7 +2754,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) { if (N1C && N0.getOpcode() == ISD::CTLZ && N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { APInt KnownZero, KnownOne; - APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); + APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); // If any of the input bits are KnownOne, then the input couldn't be all diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index e4d123f3f65..81f28adc0d8 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -1080,8 +1080,8 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue Amt = N->getOperand(1); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); EVT ShTy = Amt.getValueType(); - unsigned ShBits = ShTy.getSizeInBits(); - unsigned NVTBits = NVT.getSizeInBits(); + unsigned ShBits = ShTy.getScalarType().getSizeInBits(); + unsigned NVTBits = NVT.getScalarType().getSizeInBits(); assert(isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"); DebugLoc dl = N->getDebugLoc(); diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index eca9f3f1c88..0e54ca44aa5 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1608,7 +1608,7 @@ static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { // Fall back to ComputeMaskedBits to catch other known cases. EVT OpVT = Val.getValueType(); - unsigned BitWidth = OpVT.getSizeInBits(); + unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); APInt Mask = APInt::getAllOnesValue(BitWidth); APInt KnownZero, KnownOne; DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); diff --git a/test/CodeGen/X86/vec_cast.ll b/test/CodeGen/X86/vec_cast.ll index 1f899b3c20a..6f18d13cc9d 100644 --- a/test/CodeGen/X86/vec_cast.ll +++ b/test/CodeGen/X86/vec_cast.ll @@ -31,11 +31,10 @@ define <1 x i32> @f(<1 x i16> %a) nounwind { ret <1 x i32> %c } -; TODO: Legalize doesn't yet handle this. -;define <8 x i16> @g(<8 x i32> %a) nounwind { -; %c = trunc <8 x i32> %a to <8 x i16> -; ret <8 x i16> %c -;} +define <8 x i16> @g(<8 x i32> %a) nounwind { + %c = trunc <8 x i32> %a to <8 x i16> + ret <8 x i16> %c +} define <3 x i16> @h(<3 x i32> %a) nounwind { %c = trunc <3 x i32> %a to <3 x i16> @@ -46,3 +45,12 @@ define <1 x i16> @i(<1 x i32> %a) nounwind { %c = trunc <1 x i32> %a to <1 x i16> ret <1 x i16> %c } + +; PR6438 +define void @__OpenCL_math_kernel4_kernel() nounwind { + %tmp12.i = and <4 x i32> zeroinitializer, ; <<4 x i32>> [#uses=1] + %cmp13.i = icmp eq <4 x i32> %tmp12.i, ; <<4 x i1>> [#uses=2] + %cmp.ext14.i = sext <4 x i1> %cmp13.i to <4 x i32> ; <<4 x i32>> [#uses=0] + %tmp2110.i = and <4 x i1> %cmp13.i, zeroinitializer ; <<4 x i1>> [#uses=0] + ret void +} -- 2.34.1