From 55c790e29c334af76790f6ee01df6b0575f668ec Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Thu, 3 Dec 2015 16:47:20 +0000 Subject: [PATCH] [Hexagon] Implement CONCAT_VECTORS for HVX using V6_vcombine git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254617 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonISelLowering.cpp | 10 ++++++++++ lib/Target/Hexagon/HexagonISelLowering.h | 1 + lib/Target/Hexagon/HexagonInstrInfoV60.td | 16 +++++++++++++++- 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index 04f5b664929..a75f391a4ee 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2042,6 +2042,7 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ"; case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT"; case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU"; + case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE"; case HexagonISD::VSHLH: return "HexagonISD::VSHLH"; case HexagonISD::VSHLW: return "HexagonISD::VSHLW"; case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB"; @@ -2346,6 +2347,7 @@ SDValue HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); + bool UseHVX = Subtarget.useHVXOps(); EVT VT = Op.getValueType(); unsigned NElts = Op.getNumOperands(); SDValue Vec = Op.getOperand(0); @@ -2376,6 +2378,14 @@ HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op, } } + if (UseHVX) { + SDValue Vec0 = Op.getOperand(1); + uint64_t VS = VecVT.getSizeInBits(); + assert((VS == 64*8 && Subtarget.useHVXSglOps()) || + (VS == 128*8 && Subtarget.useHVXDblOps())); + SDValue Combined = DAG.getNode(HexagonISD::VCOMBINE, dl, VT, Vec0, Vec); + return Combined; + } for (unsigned i = 0, e = NElts; i != e; ++i) { unsigned OpIdx = NElts - i - 1; SDValue Operand = Op.getOperand(OpIdx); diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 64033d95ee3..b6d39fe9172 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -80,6 +80,7 @@ bool isPositiveHalfWord(SDNode *N); INSERTRP, EXTRACTU, EXTRACTURP, + VCOMBINE, TC_RETURN, EH_RETURN, DCFETCH, diff --git a/lib/Target/Hexagon/HexagonInstrInfoV60.td b/lib/Target/Hexagon/HexagonInstrInfoV60.td index 394df0fdd6e..897ada08153 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV60.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV60.td @@ -1535,6 +1535,20 @@ let isRegSequence = 1, Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in defm V6_vcombine : T_HVX_alu_WV <"$dst = vcombine($src1,$src2)">, V6_vcombine_enc; +def SDTHexagonVCOMBINE: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, + SDTCisSubVecOfVec<1, 0>]>; + +def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>; + +def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs), + (v16i32 VectorRegs:$Vt))), + (V6_vcombine VectorRegs:$Vs, VectorRegs:$Vt)>, + Requires<[UseHVXSgl]>; +def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs), + (v32i32 VecDblRegs:$Vt))), + (V6_vcombine_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>, + Requires<[UseHVXDbl]>; + let Itinerary = CVI_VINLANESAT, Type = TypeCVI_VINLANESAT in { defm V6_vsathub : T_HVX_alu_VV <"$dst.ub = vsat($src1.h,$src2.h)">, V6_vsathub_enc; @@ -1872,7 +1886,7 @@ defm V6_vasrhbrndsat : V6_vasrhbrndsat_enc; } -// Assemlber mapped -- alias? +// Assembler mapped -- alias? //defm V6_vtran2x2vdd : T_HVX_shift_VV <"">, V6_vtran2x2vdd_enc; let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in { defm V6_vshuffvdd : -- 2.34.1