From 50dd1d028021bd7fd8bca3f33633ea59577c9d5e Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Mon, 11 Aug 2008 23:46:25 +0000 Subject: [PATCH] Some fixes for x86-64 JIT. Make it use small code model, except for external calls; this makes addressing modes PC-relative. Incomplete. The assertion at the top of Emitter::runOnMachineFunction was obviously bogus (always true) so I removed it. If someone knows what the correct test should be to cover all the various targets, please fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54656 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/ExecutionEngine/JIT/JITEmitter.cpp | 13 +++++++++++++ lib/Target/X86/X86CodeEmitter.cpp | 20 ++++++++------------ lib/Target/X86/X86ISelDAGToDAG.cpp | 22 ++++++++++++++++++++++ lib/Target/X86/X86TargetMachine.cpp | 8 +++++--- 4 files changed, 48 insertions(+), 15 deletions(-) diff --git a/lib/ExecutionEngine/JIT/JITEmitter.cpp b/lib/ExecutionEngine/JIT/JITEmitter.cpp index d38f9f90e20..3100f0680b7 100644 --- a/lib/ExecutionEngine/JIT/JITEmitter.cpp +++ b/lib/ExecutionEngine/JIT/JITEmitter.cpp @@ -920,9 +920,22 @@ bool JITEmitter::finishFunction(MachineFunction &F) { Relocations.clear(); #ifndef NDEBUG + { + DOUT << std::hex; + int i; + unsigned char* q = FnStart; + for (i=1; q!=FnEnd; q++, i++) { + if (i%8==1) + DOUT << "0x" << (long)q << ": "; + DOUT<< (unsigned short)*q << " "; + if (i%8==0) + DOUT<<"\n"; + } + DOUT << std::dec; if (sys::hasDisassembler()) DOUT << "Disassembled code:\n" << sys::disassembleBuffer(FnStart, FnEnd-FnStart, (uintptr_t)FnStart); + } #endif if (ExceptionHandling) { uintptr_t ActualSize = 0; diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 1b2d5ffc3e6..c0d051fcefe 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -106,10 +106,7 @@ FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM, } bool Emitter::runOnMachineFunction(MachineFunction &MF) { - assert((MF.getTarget().getRelocationModel() != Reloc::Default || - MF.getTarget().getRelocationModel() != Reloc::Static) && - "JIT relocation model must be set to static or default!"); - + MCE.setModuleInfo(&getAnalysis()); II = TM.getInstrInfo(); @@ -517,11 +514,16 @@ void Emitter::emitInstruction(const MachineInstr &MI, if (CurOp != NumOps) { const MachineOperand &MO = MI.getOperand(CurOp++); +DOUT << "RawFrm CurOp " << CurOp << "\n"; +DOUT << "isMachineBasicBlock " << MO.isMachineBasicBlock() << "\n"; +DOUT << "isGlobalAddress " << MO.isGlobalAddress() << "\n"; +DOUT << "isExternalSymbol " << MO.isExternalSymbol() << "\n"; +DOUT << "isImmediate " << MO.isImmediate() << "\n"; if (MO.isMachineBasicBlock()) { emitPCRelativeBlockAddress(MO.getMBB()); } else if (MO.isGlobalAddress()) { - bool NeedStub = (Is64BitMode && TM.getCodeModel() == CodeModel::Large) - || Opcode == X86::TAILJMPd; + // Assume undefined functions may be outside the Small codespace. + bool NeedStub = Is64BitMode || Opcode == X86::TAILJMPd; emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word, 0, 0, NeedStub); } else if (MO.isExternalSymbol()) { @@ -545,8 +547,6 @@ void Emitter::emitInstruction(const MachineInstr &MI, else { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); - if (Opcode == X86::MOV64ri) - rt = X86::reloc_absolute_dword; // FIXME: add X86II flag? if (MO1.isGlobalAddress()) { bool NeedStub = isa(MO1.getGlobal()); bool isLazy = gvNeedsLazyPtr(MO1.getGlobal()); @@ -617,8 +617,6 @@ void Emitter::emitInstruction(const MachineInstr &MI, else { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); - if (Opcode == X86::MOV64ri32) - rt = X86::reloc_absolute_word; // FIXME: add X86II flag? if (MO1.isGlobalAddress()) { bool NeedStub = isa(MO1.getGlobal()); bool isLazy = gvNeedsLazyPtr(MO1.getGlobal()); @@ -654,8 +652,6 @@ void Emitter::emitInstruction(const MachineInstr &MI, else { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); - if (Opcode == X86::MOV64mi32) - rt = X86::reloc_absolute_word; // FIXME: add X86II flag? if (MO.isGlobalAddress()) { bool NeedStub = isa(MO.getGlobal()); bool isLazy = gvNeedsLazyPtr(MO.getGlobal()); diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index e9fefcbf5f1..7834f6e1fda 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -35,6 +35,7 @@ #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/Streams.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" #include @@ -77,6 +78,23 @@ namespace { : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0), GV(0), CP(0), ES(0), JT(-1), Align(0) { } + void dump() { + cerr << "X86ISelAddressMode " << this << "\n"; + cerr << "Base.Reg "; if (Base.Reg.Val!=0) Base.Reg.Val->dump(); + else cerr << "nul"; + cerr << " Base.FrameIndex " << Base.FrameIndex << "\n"; + cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n"; + cerr << "IndexReg "; if (IndexReg.Val!=0) IndexReg.Val->dump(); + else cerr << "nul"; + cerr << " Disp " << Disp << "\n"; + cerr << "GV "; if (GV) GV->dump(); + else cerr << "nul"; + cerr << " CP "; if (CP) CP->dump(); + else cerr << "nul"; + cerr << "\n"; + cerr << "ES "; if (ES) cerr << ES; else cerr << "nul"; + cerr << " JT" << JT << " Align" << Align << "\n"; + } }; } @@ -676,6 +694,7 @@ void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) { /// addressing mode. bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM, bool isRoot, unsigned Depth) { +DOUT << "MatchAddress: "; DEBUG(AM.dump()); // Limit recursion. if (Depth > 5) return MatchAddressBase(N, AM, isRoot, Depth); @@ -707,6 +726,9 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM, } case X86ISD::Wrapper: { +DOUT << "Wrapper: 64bit " << Subtarget->is64Bit(); +DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n"; +DOUT << "AlreadySelected " << AlreadySelected << "\n"; bool is64Bit = Subtarget->is64Bit(); // Under X86-64 non-small code model, GV (and friends) are 64-bits. // Also, base and index reg must be 0 in order to use rip as base. diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index e163956f3e4..8e10ee9b225 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -194,12 +194,14 @@ bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast, bool DumpAsm, MachineCodeEmitter &MCE) { // FIXME: Move this to TargetJITInfo! - if (DefRelocModel == Reloc::Default) + // Do not override 64-bit setting made in X86TargetMachine(). + if (DefRelocModel == Reloc::Default && !Subtarget.is64Bit()) setRelocationModel(Reloc::Static); - // JIT cannot ensure globals are placed in the lower 4G of address. + // 64-bit JIT places everything in the same buffer except external functions. + // Use small code model but hack the call instruction for externals. if (Subtarget.is64Bit()) - setCodeModel(CodeModel::Large); + setCodeModel(CodeModel::Small); PM.add(createX86CodeEmitterPass(*this, MCE)); if (DumpAsm) -- 2.34.1