From 4ad9b914ee1a704b3575ba37e5f50f2816089b34 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 17 Sep 2014 17:48:32 +0000 Subject: [PATCH] R600/SI: Remove assert Since read2 / write2 are emitted for 4-byte aligned 8-byte accesses, these are seen by the scheduler. The DAG scheduler is semi-deprecated, so just ignore these for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217969 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrInfo.cpp | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 17afd831a84..b79286f810d 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -89,12 +89,6 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, if (isDS(Opc0) && isDS(Opc1)) { assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1)); - // TODO: Also shouldn't see read2st - assert(Opc0 != AMDGPU::DS_READ2_B32 && - Opc0 != AMDGPU::DS_READ2_B64 && - Opc1 != AMDGPU::DS_READ2_B32 && - Opc1 != AMDGPU::DS_READ2_B64); - // Check base reg. if (Load0->getOperand(1) != Load1->getOperand(1)) return false; @@ -103,6 +97,13 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, if (findChainOperand(Load0) != findChainOperand(Load1)) return false; + // Skip read2 / write2 variants for simplicity. + // TODO: We should report true if the used offsets are adjacent (excluded + // st64 versions). + if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 || + AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) + return false; + Offset0 = cast(Load0->getOperand(2))->getZExtValue(); Offset1 = cast(Load1->getOperand(2))->getZExtValue(); return true; -- 2.34.1