From 4396f5d9d2c215988f9368e94bfd5e1eb1cced58 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Tue, 28 Jan 2014 23:12:42 +0000 Subject: [PATCH] Change MCStreamer EmitInstruction interface to take subtarget info git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200345 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/AsmPrinter.h | 6 ++ include/llvm/MC/MCObjectStreamer.h | 2 +- include/llvm/MC/MCStreamer.h | 2 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 11 ++- lib/LTO/LTOModule.cpp | 2 +- lib/MC/MCAsmStreamer.cpp | 4 +- lib/MC/MCNullStreamer.cpp | 2 +- lib/MC/MCObjectStreamer.cpp | 2 +- lib/Target/AArch64/AArch64AsmPrinter.cpp | 2 +- .../AArch64/AsmParser/AArch64AsmParser.cpp | 4 +- .../MCTargetDesc/AArch64ELFStreamer.cpp | 4 +- lib/Target/ARM/ARMAsmPrinter.cpp | 86 +++++++++---------- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- .../ARM/MCTargetDesc/ARMELFStreamer.cpp | 4 +- lib/Target/Hexagon/HexagonAsmPrinter.cpp | 4 +- lib/Target/MSP430/MSP430AsmPrinter.cpp | 2 +- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 2 +- lib/Target/Mips/MipsAsmPrinter.cpp | 2 +- lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 2 +- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 2 +- lib/Target/PowerPC/PPCAsmPrinter.cpp | 64 +++++++------- lib/Target/R600/AMDGPUMCInstLower.cpp | 2 +- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 2 +- lib/Target/Sparc/SparcAsmPrinter.cpp | 52 ++++++----- .../SystemZ/AsmParser/SystemZAsmParser.cpp | 2 +- lib/Target/SystemZ/SystemZAsmPrinter.cpp | 2 +- lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 +- lib/Target/X86/X86MCInstLower.cpp | 55 ++++++------ lib/Target/XCore/XCoreAsmPrinter.cpp | 2 +- tools/llvm-mc/Disassembler.cpp | 7 +- utils/TableGen/PseudoLoweringEmitter.cpp | 2 +- 31 files changed, 184 insertions(+), 159 deletions(-) diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h index 85f4130a2fa..f83d96783c7 100644 --- a/include/llvm/CodeGen/AsmPrinter.h +++ b/include/llvm/CodeGen/AsmPrinter.h @@ -42,6 +42,7 @@ namespace llvm { class MCAsmInfo; class MCCFIInstruction; class MCContext; + class MCInst; class MCInstrInfo; class MCSection; class MCStreamer; @@ -149,6 +150,11 @@ namespace llvm { /// getDataLayout - Return information about data layout. const DataLayout &getDataLayout() const; + /// getSubtargetInfo - Return information about subtarget. + const MCSubtargetInfo &getSubtargetInfo() const; + + void EmitToStreamer(MCStreamer &S, const MCInst &Inst); + /// getTargetTriple - Return the target triple string. StringRef getTargetTriple() const; diff --git a/include/llvm/MC/MCObjectStreamer.h b/include/llvm/MC/MCObjectStreamer.h index f6a7e713c4c..6ad7fa19237 100644 --- a/include/llvm/MC/MCObjectStreamer.h +++ b/include/llvm/MC/MCObjectStreamer.h @@ -83,7 +83,7 @@ public: virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol); virtual void ChangeSection(const MCSection *Section, const MCExpr *Subsection); - virtual void EmitInstruction(const MCInst &Inst); + virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo& STI); /// \brief Emit an instruction to a special fragment, because this instruction /// can change its size during relaxation. diff --git a/include/llvm/MC/MCStreamer.h b/include/llvm/MC/MCStreamer.h index 9a4bafe3cd7..3eb5446f530 100644 --- a/include/llvm/MC/MCStreamer.h +++ b/include/llvm/MC/MCStreamer.h @@ -663,7 +663,7 @@ public: /// EmitInstruction - Emit the given @p Instruction into the current /// section. - virtual void EmitInstruction(const MCInst &Inst) = 0; + virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) = 0; /// \brief Set the bundle alignment mode from now on in the section. /// The argument is the power of 2 to which the alignment is set. The diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 0eee777e123..c5726633d2a 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -48,6 +48,7 @@ #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Transforms/Utils/GlobalStatus.h" #include "WinCodeViewLineTables.h" using namespace llvm; @@ -137,6 +138,14 @@ const DataLayout &AsmPrinter::getDataLayout() const { return *TM.getDataLayout(); } +const MCSubtargetInfo &AsmPrinter::getSubtargetInfo() const { + return TM.getSubtarget(); +} + +void AsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { + S.EmitInstruction(Inst, getSubtargetInfo()); +} + StringRef AsmPrinter::getTargetTriple() const { return TM.getTargetTriple(); } @@ -789,7 +798,7 @@ void AsmPrinter::EmitFunctionBody() { TM.getInstrInfo()->getNoopForMachoTarget(Noop); if (Noop.getOpcode()) { OutStreamer.AddComment("avoids zero-length function"); - OutStreamer.EmitInstruction(Noop); + OutStreamer.EmitInstruction(Noop, getSubtargetInfo()); } else // Target not mc-ized yet. OutStreamer.EmitRawText(StringRef("\tnop\n")); } diff --git a/lib/LTO/LTOModule.cpp b/lib/LTO/LTOModule.cpp index c1a9f80b528..669ccbbaab4 100644 --- a/lib/LTO/LTOModule.cpp +++ b/lib/LTO/LTOModule.cpp @@ -625,7 +625,7 @@ namespace { RecordStreamer(MCContext &Context) : MCStreamer(Context) {} - virtual void EmitInstruction(const MCInst &Inst) { + virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { // Scan for values. for (unsigned i = Inst.getNumOperands(); i--; ) if (Inst.getOperand(i).isExpr()) diff --git a/lib/MC/MCAsmStreamer.cpp b/lib/MC/MCAsmStreamer.cpp index d63716a815e..0a8c7f5d7eb 100644 --- a/lib/MC/MCAsmStreamer.cpp +++ b/lib/MC/MCAsmStreamer.cpp @@ -246,7 +246,7 @@ public: virtual void EmitWin64EHPushFrame(bool Code); virtual void EmitWin64EHEndProlog(); - virtual void EmitInstruction(const MCInst &Inst); + virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI); virtual void EmitBundleAlignMode(unsigned AlignPow2); virtual void EmitBundleLock(bool AlignToEnd); @@ -1318,7 +1318,7 @@ void MCAsmStreamer::AddEncodingComment(const MCInst &Inst) { } } -void MCAsmStreamer::EmitInstruction(const MCInst &Inst) { +void MCAsmStreamer::EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { assert(getCurrentSection().first && "Cannot emit contents before setting section!"); diff --git a/lib/MC/MCNullStreamer.cpp b/lib/MC/MCNullStreamer.cpp index 21339078063..7f780a36ee5 100644 --- a/lib/MC/MCNullStreamer.cpp +++ b/lib/MC/MCNullStreamer.cpp @@ -92,7 +92,7 @@ namespace { unsigned Column, unsigned Flags, unsigned Isa, unsigned Discriminator, StringRef FileName) {} - virtual void EmitInstruction(const MCInst &Inst) {} + virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo&) {} virtual void EmitBundleAlignMode(unsigned AlignPow2) {} virtual void EmitBundleLock(bool AlignToEnd) {} diff --git a/lib/MC/MCObjectStreamer.cpp b/lib/MC/MCObjectStreamer.cpp index 22f565f34e0..5aa1486b847 100644 --- a/lib/MC/MCObjectStreamer.cpp +++ b/lib/MC/MCObjectStreamer.cpp @@ -187,7 +187,7 @@ void MCObjectStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { Symbol->setVariableValue(AddValueSymbols(Value)); } -void MCObjectStreamer::EmitInstruction(const MCInst &Inst) { +void MCObjectStreamer::EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { // Scan for values. for (unsigned i = Inst.getNumOperands(); i--; ) if (Inst.getOperand(i).isExpr()) diff --git a/lib/Target/AArch64/AArch64AsmPrinter.cpp b/lib/Target/AArch64/AArch64AsmPrinter.cpp index 83de250ba13..c5d73f09e4c 100644 --- a/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -264,7 +264,7 @@ void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst TmpInst; LowerAArch64MachineInstrToMCInst(MI, TmpInst, *this); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); } void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) { diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 7afcd4d4146..5a70400023f 100644 --- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2375,7 +2375,7 @@ bool AArch64AsmParser::ParseDirectiveTLSDescCall(SMLoc L) { Inst.setOpcode(AArch64::TLSDESCCALL); Inst.addOperand(MCOperand::CreateExpr(Expr)); - getParser().getStreamer().EmitInstruction(Inst); + getParser().getStreamer().EmitInstruction(Inst, STI); return false; } @@ -2398,7 +2398,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, if (validateInstruction(Inst, Operands)) return true; - Out.EmitInstruction(Inst); + Out.EmitInstruction(Inst, STI); return false; case Match_MissingFeature: Error(IDLoc, "instruction requires a CPU feature not currently enabled"); diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp index 6e680bdabbc..473b7dda004 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp @@ -76,9 +76,9 @@ public: /// This function is the one used to emit instruction data into the ELF /// streamer. We override it to add the appropriate mapping symbol if /// necessary. - virtual void EmitInstruction(const MCInst& Inst) { + virtual void EmitInstruction(const MCInst& Inst, const MCSubtargetInfo &STI) { EmitA64MappingSymbol(); - MCELFStreamer::EmitInstruction(Inst); + MCELFStreamer::EmitInstruction(Inst, STI); } /// This is one of the functions used to emit data into an ELF section, so the diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 4d52ec5409f..9c40ac8a7a4 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -939,7 +939,7 @@ void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) { OutContext); // If this isn't a TBB or TBH, the entries are direct branch instructions. if (OffsetWidth == 4) { - OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B) .addExpr(MBBSymbolExpr) .addImm(ARMCC::AL) .addReg(0)); @@ -1142,7 +1142,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::t2LEApcrel: { // FIXME: Need to also handle globals and externals MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex()); - OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() == + EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR : ARM::ADR)) @@ -1159,7 +1159,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCSymbol *JTIPICSymbol = GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(), MI->getOperand(2).getImm()); - OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() == + EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR : ARM::ADR)) @@ -1173,7 +1173,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // Darwin call instructions are just normal call instructions with different // clobber semantics (they clobber R9). case ARM::BX_CALL: { - OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr) .addReg(ARM::LR) .addReg(ARM::PC) // Add predicate operands. @@ -1182,19 +1182,19 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // Add 's' bit operand (always reg0 for this) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX) .addReg(MI->getOperand(0).getReg())); return; } case ARM::tBX_CALL: { - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr) .addReg(ARM::LR) .addReg(ARM::PC) // Add predicate operands. .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX) .addReg(MI->getOperand(0).getReg()) // Add predicate operands. .addImm(ARMCC::AL) @@ -1202,7 +1202,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case ARM::BMOVPCRX_CALL: { - OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr) .addReg(ARM::LR) .addReg(ARM::PC) // Add predicate operands. @@ -1211,7 +1211,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // Add 's' bit operand (always reg0 for this) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr) .addReg(ARM::PC) .addReg(MI->getOperand(0).getReg()) // Add predicate operands. @@ -1222,7 +1222,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case ARM::BMOVPCB_CALL: { - OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr) .addReg(ARM::LR) .addReg(ARM::PC) // Add predicate operands. @@ -1234,7 +1234,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { const GlobalValue *GV = MI->getOperand(0).getGlobal(); MCSymbol *GVSym = getSymbol(GV); const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc) .addExpr(GVSymExpr) // Add predicate operands. .addImm(ARMCC::AL) @@ -1269,7 +1269,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { TmpInst.addOperand(MCOperand::CreateReg(0)); // Add 's' bit operand (always reg0 for this) TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); return; } case ARM::MOVTi16_ga_pcrel: @@ -1301,7 +1301,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { TmpInst.addOperand(MCOperand::CreateReg(0)); // Add 's' bit operand (always reg0 for this) TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); return; } case ARM::tPICADD: { @@ -1316,7 +1316,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutContext)); // Form and emit the add. - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr) .addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg()) .addReg(ARM::PC) @@ -1337,7 +1337,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutContext)); // Form and emit the add. - OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr) .addReg(MI->getOperand(0).getReg()) .addReg(ARM::PC) .addReg(MI->getOperand(1).getReg()) @@ -1381,7 +1381,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; } - OutStreamer.EmitInstruction(MCInstBuilder(Opcode) + EmitToStreamer(OutStreamer, MCInstBuilder(Opcode) .addReg(MI->getOperand(0).getReg()) .addReg(ARM::PC) .addReg(MI->getOperand(1).getReg()) @@ -1418,7 +1418,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case ARM::t2BR_JT: { // Lower and emit the instruction itself, then the jump table following it. - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr) .addReg(ARM::PC) .addReg(MI->getOperand(0).getReg()) // Add predicate operands. @@ -1431,7 +1431,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case ARM::t2TBB_JT: { // Lower and emit the instruction itself, then the jump table following it. - OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB) .addReg(ARM::PC) .addReg(MI->getOperand(0).getReg()) // Add predicate operands. @@ -1446,7 +1446,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case ARM::t2TBH_JT: { // Lower and emit the instruction itself, then the jump table following it. - OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH) .addReg(ARM::PC) .addReg(MI->getOperand(0).getReg()) // Add predicate operands. @@ -1473,7 +1473,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // Add 's' bit operand (always reg0 for this) if (Opc == ARM::MOVr) TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); // Make sure the Thumb jump table is 4-byte aligned. if (Opc == ARM::tMOVr) @@ -1503,7 +1503,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // Add predicate operands. TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); // Output the data for the jump table itself EmitJumpTable(MI); @@ -1512,7 +1512,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::BR_JTadd: { // Lower and emit the instruction itself, then the jump table following it. // add pc, target, idx - OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr) .addReg(ARM::PC) .addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()) @@ -1572,14 +1572,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned ValReg = MI->getOperand(1).getReg(); MCSymbol *Label = GetARMSJLJEHLabel(); OutStreamer.AddComment("eh_setjmp begin"); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr) .addReg(ValReg) .addReg(ARM::PC) // Predicate. .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3) .addReg(ValReg) // 's' bit operand .addReg(ARM::CPSR) @@ -1589,7 +1589,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi) .addReg(ValReg) .addReg(SrcReg) // The offset immediate is #4. The operand value is scaled by 4 for the @@ -1599,7 +1599,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8) .addReg(ARM::R0) .addReg(ARM::CPSR) .addImm(0) @@ -1608,13 +1608,13 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addReg(0)); const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB) .addExpr(SymbolExpr) .addImm(ARMCC::AL) .addReg(0)); OutStreamer.AddComment("eh_setjmp end"); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8) .addReg(ARM::R0) .addReg(ARM::CPSR) .addImm(1) @@ -1638,7 +1638,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned ValReg = MI->getOperand(1).getReg(); OutStreamer.AddComment("eh_setjmp begin"); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri) .addReg(ValReg) .addReg(ARM::PC) .addImm(8) @@ -1648,7 +1648,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // 's' bit operand (always reg0 for this). .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12) .addReg(ValReg) .addReg(SrcReg) .addImm(4) @@ -1656,7 +1656,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi) .addReg(ARM::R0) .addImm(0) // Predicate. @@ -1665,7 +1665,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // 's' bit operand (always reg0 for this). .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri) .addReg(ARM::PC) .addReg(ARM::PC) .addImm(0) @@ -1676,7 +1676,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addReg(0)); OutStreamer.AddComment("eh_setjmp end"); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi) .addReg(ARM::R0) .addImm(1) // Predicate. @@ -1693,7 +1693,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // bx $scratch unsigned SrcReg = MI->getOperand(0).getReg(); unsigned ScratchReg = MI->getOperand(1).getReg(); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12) .addReg(ARM::SP) .addReg(SrcReg) .addImm(8) @@ -1701,7 +1701,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12) .addReg(ScratchReg) .addReg(SrcReg) .addImm(4) @@ -1709,7 +1709,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12) .addReg(ARM::R7) .addReg(SrcReg) .addImm(0) @@ -1717,7 +1717,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX) .addReg(ScratchReg) // Predicate. .addImm(ARMCC::AL) @@ -1732,7 +1732,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // bx $scratch unsigned SrcReg = MI->getOperand(0).getReg(); unsigned ScratchReg = MI->getOperand(1).getReg(); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi) .addReg(ScratchReg) .addReg(SrcReg) // The offset immediate is #8. The operand value is scaled by 4 for the @@ -1742,14 +1742,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr) .addReg(ARM::SP) .addReg(ScratchReg) // Predicate. .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi) .addReg(ScratchReg) .addReg(SrcReg) .addImm(1) @@ -1757,7 +1757,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi) .addReg(ARM::R7) .addReg(SrcReg) .addImm(0) @@ -1765,7 +1765,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0)); - OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX) + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX) .addReg(ScratchReg) // Predicate. .addImm(ARMCC::AL) @@ -1777,7 +1777,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst TmpInst; LowerARMMachineInstrToMCInst(MI, TmpInst, *this); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); } //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 4577fdee37e..2f9a12f2c77 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -7972,7 +7972,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return false; Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst); + Out.EmitInstruction(Inst, STI); return false; case Match_MissingFeature: { assert(ErrorInfo && "Unknown missing feature!"); diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index 707a3d3f2ed..efee318a047 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -458,13 +458,13 @@ public: /// This function is the one used to emit instruction data into the ELF /// streamer. We override it to add the appropriate mapping symbol if /// necessary. - virtual void EmitInstruction(const MCInst& Inst) { + virtual void EmitInstruction(const MCInst& Inst, const MCSubtargetInfo &STI) { if (IsThumb) EmitThumbMappingSymbol(); else EmitARMMappingSymbol(); - MCELFStreamer::EmitInstruction(Inst); + MCELFStreamer::EmitInstruction(Inst, STI); } virtual void emitInst(uint32_t Inst, char Suffix) { diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 7757394c8f7..a5882747eb0 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -199,7 +199,7 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCI.setPacketEnd(Index == (Size-1)); HexagonLowerToMC(BundleMIs[Index], MCI, *this); - OutStreamer.EmitInstruction(MCI); + EmitToStreamer(OutStreamer, MCI); } } else { @@ -209,7 +209,7 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCI.setPacketEnd(true); } HexagonLowerToMC(MI, MCI, *this); - OutStreamer.EmitInstruction(MCI); + EmitToStreamer(OutStreamer, MCI); } return; diff --git a/lib/Target/MSP430/MSP430AsmPrinter.cpp b/lib/Target/MSP430/MSP430AsmPrinter.cpp index 92d86497858..91065d86bc1 100644 --- a/lib/Target/MSP430/MSP430AsmPrinter.cpp +++ b/lib/Target/MSP430/MSP430AsmPrinter.cpp @@ -151,7 +151,7 @@ void MSP430AsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); } // Force static initialization. diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 74e4fffceea..7e5706b3d1e 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -906,7 +906,7 @@ bool MipsAsmParser::MatchAndEmitInstruction( if (processInstruction(Inst, IDLoc, Instructions)) return true; for (unsigned i = 0; i < Instructions.size(); i++) - Out.EmitInstruction(Instructions[i]); + Out.EmitInstruction(Instructions[i], STI); return false; } case Match_MissingFeature: diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp index 40a30293738..a5ac2ab8bc4 100644 --- a/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/MipsAsmPrinter.cpp @@ -131,7 +131,7 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst TmpInst0; MCInstLowering.Lower(I, TmpInst0); - OutStreamer.EmitInstruction(TmpInst0); + EmitToStreamer(OutStreamer, TmpInst0); } while ((++I != E) && I->isInsideBundle()); // Delay slot check } diff --git a/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/lib/Target/NVPTX/NVPTXAsmPrinter.cpp index 5fad27e47a9..7d3f3a2359e 100644 --- a/lib/Target/NVPTX/NVPTXAsmPrinter.cpp +++ b/lib/Target/NVPTX/NVPTXAsmPrinter.cpp @@ -307,7 +307,7 @@ void NVPTXAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst Inst; lowerToMCInst(MI, Inst); - OutStreamer.EmitInstruction(Inst); + EmitToStreamer(OutStreamer, Inst); } void NVPTXAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) { diff --git a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 1d8c10cd7b9..b76416c6334 100644 --- a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -873,7 +873,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, // Post-process instructions (typically extended mnemonics) ProcessInstruction(Inst, Operands); Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst); + Out.EmitInstruction(Inst, STI); return false; case Match_MissingFeature: return Error(IDLoc, "instruction use requires an option to be enabled"); diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 786c4f9a334..fb5dbf272ed 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -317,7 +317,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCSymbol *PICBase = MF->getPICBaseSymbol(); // Emit the 'bl'. - OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL) // FIXME: We would like an efficient form for this, so we don't have to do // a lot of extra uniquing. .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext))); @@ -353,7 +353,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_PPC_TOC, OutContext); TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); return; } @@ -399,7 +399,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_HA, OutContext); TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); return; } case PPC::LDtocL: { @@ -440,7 +440,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO, OutContext); TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); return; } case PPC::ADDItocL: { @@ -476,7 +476,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO, OutContext); TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); return; } case PPC::ADDISgotTprelHA: { @@ -489,7 +489,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymGotTprel = MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL_HA, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8) .addReg(MI->getOperand(0).getReg()) .addReg(PPC::X2) .addExpr(SymGotTprel)); @@ -509,7 +509,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO, OutContext); TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); return; } @@ -521,10 +521,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymGotTlsHA = MCSymbolRefExpr::Create(GOTSymbol, MCSymbolRefExpr::VK_PPC_HA, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::LI) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::LI) .addReg(MI->getOperand(0).getReg()) .addExpr(SymGotTlsL)); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS) .addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg()) .addExpr(SymGotTlsHA)); @@ -540,7 +540,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymGotTlsGD = MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD_HA, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8) .addReg(MI->getOperand(0).getReg()) .addReg(PPC::X2) .addExpr(SymGotTlsGD)); @@ -556,7 +556,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymGotTlsGD = MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8) .addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()) .addExpr(SymGotTlsGD)); @@ -577,7 +577,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymVar = MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSGD, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL8_NOP_TLS) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL8_NOP_TLS) .addExpr(TlsRef) .addExpr(SymVar)); return; @@ -592,7 +592,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymGotTlsLD = MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD_HA, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8) .addReg(MI->getOperand(0).getReg()) .addReg(PPC::X2) .addExpr(SymGotTlsLD)); @@ -608,7 +608,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymGotTlsLD = MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8) .addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()) .addExpr(SymGotTlsLD)); @@ -629,7 +629,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymVar = MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSLD, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL8_NOP_TLS) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL8_NOP_TLS) .addExpr(TlsRef) .addExpr(SymVar)); return; @@ -644,7 +644,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymDtprel = MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_HA, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8) .addReg(MI->getOperand(0).getReg()) .addReg(PPC::X3) .addExpr(SymDtprel)); @@ -660,7 +660,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCExpr *SymDtprel = MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_LO, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8) .addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()) .addExpr(SymDtprel)); @@ -675,7 +675,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { MI->getOpcode() == PPC::MFOCRF ? PPC::MFCR : PPC::MFCR8; OutStreamer.AddComment(PPCInstPrinter:: getRegisterName(MI->getOperand(1).getReg())); - OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode) + EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode) .addReg(MI->getOperand(0).getReg())); return; } @@ -691,7 +691,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { ->getEncodingValue(MI->getOperand(0).getReg()); OutStreamer.AddComment(PPCInstPrinter:: getRegisterName(MI->getOperand(0).getReg())); - OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode) + EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode) .addImm(Mask) .addReg(MI->getOperand(1).getReg())); return; @@ -719,7 +719,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { } LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); } void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() { @@ -925,32 +925,32 @@ EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) { MCBinaryExpr::CreateSub(LazyPtrExpr, Anon, OutContext); // mflr r0 - OutStreamer.EmitInstruction(MCInstBuilder(PPC::MFLR).addReg(PPC::R0)); + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MFLR).addReg(PPC::R0)); // bcl 20, 31, AnonSymbol - OutStreamer.EmitInstruction(MCInstBuilder(PPC::BCLalways).addExpr(Anon)); + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BCLalways).addExpr(Anon)); OutStreamer.EmitLabel(AnonSymbol); // mflr r11 - OutStreamer.EmitInstruction(MCInstBuilder(PPC::MFLR).addReg(PPC::R11)); + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MFLR).addReg(PPC::R11)); // addis r11, r11, ha16(LazyPtr - AnonSymbol) const MCExpr *SubHa16 = PPCMCExpr::CreateHa(Sub, isDarwin, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS) .addReg(PPC::R11) .addReg(PPC::R11) .addExpr(SubHa16)); // mtlr r0 - OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTLR).addReg(PPC::R0)); + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MTLR).addReg(PPC::R0)); // ldu r12, lo16(LazyPtr - AnonSymbol)(r11) // lwzu r12, lo16(LazyPtr - AnonSymbol)(r11) const MCExpr *SubLo16 = PPCMCExpr::CreateLo(Sub, isDarwin, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU) + EmitToStreamer(OutStreamer, MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU) .addReg(PPC::R12) .addExpr(SubLo16).addExpr(SubLo16) .addReg(PPC::R11)); // mtctr r12 - OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12)); + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MTCTR).addReg(PPC::R12)); // bctr - OutStreamer.EmitInstruction(MCInstBuilder(PPC::BCTR)); + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BCTR)); OutStreamer.SwitchSection(LSPSection); OutStreamer.EmitLabel(LazyPtr); @@ -989,7 +989,7 @@ EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) { // lis r11, ha16(LazyPtr) const MCExpr *LazyPtrHa16 = PPCMCExpr::CreateHa(LazyPtrExpr, isDarwin, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(PPC::LIS) + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::LIS) .addReg(PPC::R11) .addExpr(LazyPtrHa16)); @@ -997,15 +997,15 @@ EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) { // lwzu r12, lo16(LazyPtr)(r11) const MCExpr *LazyPtrLo16 = PPCMCExpr::CreateLo(LazyPtrExpr, isDarwin, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU) + EmitToStreamer(OutStreamer, MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU) .addReg(PPC::R12) .addExpr(LazyPtrLo16).addExpr(LazyPtrLo16) .addReg(PPC::R11)); // mtctr r12 - OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12)); + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MTCTR).addReg(PPC::R12)); // bctr - OutStreamer.EmitInstruction(MCInstBuilder(PPC::BCTR)); + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BCTR)); OutStreamer.SwitchSection(LSPSection); OutStreamer.EmitLabel(LazyPtr); diff --git a/lib/Target/R600/AMDGPUMCInstLower.cpp b/lib/Target/R600/AMDGPUMCInstLower.cpp index 0ed598ee8c0..82ac0b4c740 100644 --- a/lib/Target/R600/AMDGPUMCInstLower.cpp +++ b/lib/Target/R600/AMDGPUMCInstLower.cpp @@ -80,7 +80,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { } else { MCInst TmpInst; MCInstLowering.lower(MI, TmpInst); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); if (DisasmEnabled) { // Disassemble instruction/operands to text. diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index a4ea265a65d..ca27b40e73b 100644 --- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -393,7 +393,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_Success: { Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst); + Out.EmitInstruction(Inst, STI); return false; } diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp index a6f4dc2b0da..50c4fb7f031 100644 --- a/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -107,48 +107,54 @@ static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, } static void EmitCall(MCStreamer &OutStreamer, - MCOperand &Callee) + MCOperand &Callee, + const MCSubtargetInfo &STI) { MCInst CallInst; CallInst.setOpcode(SP::CALL); CallInst.addOperand(Callee); - OutStreamer.EmitInstruction(CallInst); + OutStreamer.EmitInstruction(CallInst, STI); } static void EmitSETHI(MCStreamer &OutStreamer, - MCOperand &Imm, MCOperand &RD) + MCOperand &Imm, MCOperand &RD, + const MCSubtargetInfo &STI) { MCInst SETHIInst; SETHIInst.setOpcode(SP::SETHIi); SETHIInst.addOperand(RD); SETHIInst.addOperand(Imm); - OutStreamer.EmitInstruction(SETHIInst); + OutStreamer.EmitInstruction(SETHIInst, STI); } static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, - MCOperand &RS1, MCOperand &Src2, MCOperand &RD) + MCOperand &RS1, MCOperand &Src2, MCOperand &RD, + const MCSubtargetInfo &STI) { MCInst Inst; Inst.setOpcode(Opcode); Inst.addOperand(RD); Inst.addOperand(RS1); Inst.addOperand(Src2); - OutStreamer.EmitInstruction(Inst); + OutStreamer.EmitInstruction(Inst, STI); } static void EmitOR(MCStreamer &OutStreamer, - MCOperand &RS1, MCOperand &Imm, MCOperand &RD) { - EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD); + MCOperand &RS1, MCOperand &Imm, MCOperand &RD, + const MCSubtargetInfo &STI) { + EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI); } static void EmitADD(MCStreamer &OutStreamer, - MCOperand &RS1, MCOperand &RS2, MCOperand &RD) { - EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD); + MCOperand &RS1, MCOperand &RS2, MCOperand &RD, + const MCSubtargetInfo &STI) { + EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI); } static void EmitSHL(MCStreamer &OutStreamer, - MCOperand &RS1, MCOperand &Imm, MCOperand &RD) { - EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD); + MCOperand &RS1, MCOperand &Imm, MCOperand &RD, + const MCSubtargetInfo &STI) { + EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI); } @@ -156,15 +162,17 @@ static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, - MCContext &OutContext) { + MCContext &OutContext, + const MCSubtargetInfo &STI) { MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext); MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext); - EmitSETHI(OutStreamer, hi, RD); - EmitOR(OutStreamer, RD, lo, RD); + EmitSETHI(OutStreamer, hi, RD, STI); + EmitOR(OutStreamer, RD, lo, RD, STI); } -void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI) +void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, + const MCSubtargetInfo &STI) { MCSymbol *GOTLabel = OutContext.GetOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_")); @@ -232,18 +240,18 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI) OutStreamer.EmitLabel(StartLabel); MCOperand Callee = createPCXCallOP(EndLabel, OutContext); - EmitCall(OutStreamer, Callee); + EmitCall(OutStreamer, Callee, STI); OutStreamer.EmitLabel(SethiLabel); MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_HI, GOTLabel, StartLabel, SethiLabel, OutContext); - EmitSETHI(OutStreamer, hiImm, MCRegOP); + EmitSETHI(OutStreamer, hiImm, MCRegOP, STI); OutStreamer.EmitLabel(EndLabel); MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_LO, GOTLabel, StartLabel, EndLabel, OutContext); - EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP); - EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP); + EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP, STI); + EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP, STI); } void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) @@ -255,7 +263,7 @@ void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) // FIXME: Debug Value. return; case SP::GETPCX: - LowerGETPCXAndEmitMCInsts(MI); + LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo()); return; } MachineBasicBlock::const_instr_iterator I = MI; @@ -263,7 +271,7 @@ void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) do { MCInst TmpInst; LowerSparcMachineInstrToMCInst(I, TmpInst, *this); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); } while ((++I != E) && I->isInsideBundle()); // Delay slot check. } diff --git a/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp index 763f40c7ff4..e78b1a2ac7f 100644 --- a/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ b/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -715,7 +715,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, default: break; case Match_Success: Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst); + Out.EmitInstruction(Inst, STI); return false; case Match_MissingFeature: { diff --git a/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/SystemZAsmPrinter.cpp index 0fe2d1fc639..aced19ea0cc 100644 --- a/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -164,7 +164,7 @@ void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) { Lower.lower(MI, LoweredMI); break; } - OutStreamer.EmitInstruction(LoweredMI); + EmitToStreamer(OutStreamer, LoweredMI); } // Convert a SystemZ-specific constant pool modifier into the associated diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 371662bbfdc..296416ec0a2 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -2607,7 +2607,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, Inst.setOpcode(X86::WAIT); Inst.setLoc(IDLoc); if (!MatchingInlineAsm) - Out.EmitInstruction(Inst); + Out.EmitInstruction(Inst, STI); const char *Repl = StringSwitch(Op->getToken()) @@ -2643,7 +2643,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, Inst.setLoc(IDLoc); if (!MatchingInlineAsm) - Out.EmitInstruction(Inst); + Out.EmitInstruction(Inst, STI); Opcode = Inst.getOpcode(); return false; case Match_MissingFeature: { @@ -2730,7 +2730,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, if (NumSuccessfulMatches == 1) { Inst.setLoc(IDLoc); if (!MatchingInlineAsm) - Out.EmitInstruction(Inst); + Out.EmitInstruction(Inst, STI); Opcode = Inst.getOpcode(); return false; } diff --git a/lib/Target/X86/X86MCInstLower.cpp b/lib/Target/X86/X86MCInstLower.cpp index a9454cf5be8..6f88cf10595 100644 --- a/lib/Target/X86/X86MCInstLower.cpp +++ b/lib/Target/X86/X86MCInstLower.cpp @@ -602,7 +602,8 @@ ReSimplify: static void LowerTlsAddr(MCStreamer &OutStreamer, X86MCInstLower &MCInstLowering, - const MachineInstr &MI) { + const MachineInstr &MI, + const MCSubtargetInfo& STI) { bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || MI.getOpcode() == X86::TLS_base_addr64; @@ -612,7 +613,7 @@ static void LowerTlsAddr(MCStreamer &OutStreamer, MCContext &context = OutStreamer.getContext(); if (needsPadding) - OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX)); + OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); MCSymbolRefExpr::VariantKind SRVK; switch (MI.getOpcode()) { @@ -659,12 +660,12 @@ static void LowerTlsAddr(MCStreamer &OutStreamer, LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp LEA.addOperand(MCOperand::CreateReg(0)); // seg } - OutStreamer.EmitInstruction(LEA); + OutStreamer.EmitInstruction(LEA, STI); if (needsPadding) { - OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX)); - OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX)); - OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX)); + OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); + OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); + OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI); } StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; @@ -676,11 +677,11 @@ static void LowerTlsAddr(MCStreamer &OutStreamer, OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32) - .addExpr(tlsRef)); + .addExpr(tlsRef), STI); } /// \brief Emit the optimal amount of multi-byte nops on X86. -static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit) { +static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) { // This works only for 64bit. For 32bit we have to do additional checking if // the CPU supports multi-byte nops. assert(Is64Bit && "EmitNops only supports X86-64"); @@ -715,17 +716,17 @@ static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit) { switch (Opc) { default: llvm_unreachable("Unexpected opcode"); break; case X86::NOOP: - OS.EmitInstruction(MCInstBuilder(Opc)); + OS.EmitInstruction(MCInstBuilder(Opc), STI); break; case X86::XCHG16ar: - OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX)); + OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); break; case X86::NOOPL: case X86::NOOPW: OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal) .addReg(IndexReg) .addImm(Displacement) - .addReg(SegmentReg)); + .addReg(SegmentReg), STI); break; } } // while (NumBytes) @@ -734,20 +735,20 @@ static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit) { // Lower a stackmap of the form: // , , ... static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM, - const MachineInstr &MI, bool Is64Bit) { + const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) { unsigned NumBytes = MI.getOperand(1).getImm(); SM.recordStackMap(MI); // Emit padding. // FIXME: These nops ensure that the stackmap's shadow is covered by // instructions from the same basic block, but the nops should not be // necessary if instructions from the same block follow the stackmap. - EmitNops(OS, NumBytes, Is64Bit); + EmitNops(OS, NumBytes, Is64Bit, STI); } // Lower a patchpoint of the form: // [], , , , , , ... static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM, - const MachineInstr &MI, bool Is64Bit) { + const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) { assert(Is64Bit && "Patchpoint currently only supports X86-64"); SM.recordPatchPoint(MI); @@ -764,15 +765,15 @@ static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM, else EncodedBytes = 12; OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg) - .addImm(CallTarget)); - OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg)); + .addImm(CallTarget), STI); + OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI); } // Emit padding. unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm(); assert(NumBytes >= EncodedBytes && "Patchpoint can't request size less than the length of a call."); - EmitNops(OS, NumBytes - EncodedBytes, Is64Bit); + EmitNops(OS, NumBytes - EncodedBytes, Is64Bit, STI); } void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { @@ -806,7 +807,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { case X86::TLS_addr64: case X86::TLS_base_addr32: case X86::TLS_base_addr64: - return LowerTlsAddr(OutStreamer, MCInstLowering, *MI); + return LowerTlsAddr(OutStreamer, MCInstLowering, *MI, getSubtargetInfo()); case X86::MOVPC32r: { // This is a pseudo op for a two instruction sequence with a label, which @@ -819,14 +820,14 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { MCSymbol *PICBase = MF->getPICBaseSymbol(); // FIXME: We would like an efficient form for this, so we don't have to do a // lot of extra uniquing. - OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32) + EmitToStreamer(OutStreamer, MCInstBuilder(X86::CALLpcrel32) .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext))); // Emit the label. OutStreamer.EmitLabel(PICBase); // popl $reg - OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r) + EmitToStreamer(OutStreamer, MCInstBuilder(X86::POP32r) .addReg(MI->getOperand(0).getReg())); return; } @@ -857,7 +858,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), DotExpr, OutContext); - OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri) + EmitToStreamer(OutStreamer, MCInstBuilder(X86::ADD32ri) .addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()) .addExpr(DotExpr)); @@ -865,19 +866,19 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { } case TargetOpcode::STACKMAP: - return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit()); + return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo()); case TargetOpcode::PATCHPOINT: - return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit()); + return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo()); case X86::MORESTACK_RET: - OutStreamer.EmitInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); + EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget))); return; case X86::MORESTACK_RET_RESTORE_R10: // Return, then restore R10. - OutStreamer.EmitInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); - OutStreamer.EmitInstruction(MCInstBuilder(X86::MOV64rr) + EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget))); + EmitToStreamer(OutStreamer, MCInstBuilder(X86::MOV64rr) .addReg(X86::R10) .addReg(X86::RAX)); return; @@ -885,5 +886,5 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); } diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp index 38c51ed5073..fe030fa4c23 100644 --- a/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -277,7 +277,7 @@ void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); - OutStreamer.EmitInstruction(TmpInst); + EmitToStreamer(OutStreamer, TmpInst); } // Force static initialization. diff --git a/tools/llvm-mc/Disassembler.cpp b/tools/llvm-mc/Disassembler.cpp index 81a0045897a..92fc3a3f03f 100644 --- a/tools/llvm-mc/Disassembler.cpp +++ b/tools/llvm-mc/Disassembler.cpp @@ -51,7 +51,8 @@ public: static bool PrintInsts(const MCDisassembler &DisAsm, const ByteArrayTy &Bytes, SourceMgr &SM, raw_ostream &Out, - MCStreamer &Streamer, bool InAtomicBlock) { + MCStreamer &Streamer, bool InAtomicBlock, + const MCSubtargetInfo &STI) { // Wrap the vector in a MemoryObject. VectorMemoryObject memoryObject(Bytes); @@ -86,7 +87,7 @@ static bool PrintInsts(const MCDisassembler &DisAsm, // Fall through case MCDisassembler::Success: - Streamer.EmitInstruction(Inst); + Streamer.EmitInstruction(Inst, STI); break; } } @@ -202,7 +203,7 @@ int Disassembler::disassemble(const Target &T, if (!ByteArray.empty()) ErrorOccurred |= PrintInsts(*DisAsm, ByteArray, SM, Out, Streamer, - InAtomicBlock); + InAtomicBlock, STI); } if (InAtomicBlock) { diff --git a/utils/TableGen/PseudoLoweringEmitter.cpp b/utils/TableGen/PseudoLoweringEmitter.cpp index 1ea6f7932a3..100338c071a 100644 --- a/utils/TableGen/PseudoLoweringEmitter.cpp +++ b/utils/TableGen/PseudoLoweringEmitter.cpp @@ -259,7 +259,7 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) { << " if (lowerOperand(MI->getOperand(i), MCOp))\n" << " TmpInst.addOperand(MCOp);\n"; } - o << " OutStreamer.EmitInstruction(TmpInst);\n" + o << " EmitToStreamer(OutStreamer, TmpInst);\n" << " break;\n" << " }\n"; } -- 2.34.1