From 4294df4cebee381a74865a648fb4da7a10eaf828 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Fri, 21 Aug 2015 21:34:24 +0000 Subject: [PATCH] [PowerPC] PPCVSXFMAMutate should not segfault on undef input registers When PPCVSXFMAMutate would look at the input addend register, it would get its input value number. This would fail, however, if the register was undef, causing a segfault. Don't segfault (just skip such FMA instructions). Fixes the test case from PR24542 (although that may have been over-reduced). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245741 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 5 +++ test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll | 33 ++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll diff --git a/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/lib/Target/PowerPC/PPCVSXFMAMutate.cpp index 974857556dc..f392b2572bc 100644 --- a/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -103,6 +103,11 @@ protected: VNInfo *AddendValNo = LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn(); + if (!AddendValNo) { + // This can be null if the register is undef. + continue; + } + MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def); // The addend and this instruction must be in the same block. diff --git a/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll b/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll new file mode 100644 index 00000000000..e3f4001aa1d --- /dev/null +++ b/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @acosh_float8() #0 { +entry: + br i1 undef, label %if.then, label %if.end + +if.then: ; preds = %entry + %0 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef, <4 x float> , <4 x float> undef) #0 + %astype.i.i.74.i = bitcast <4 x float> %0 to <4 x i32> + %and.i.i.76.i = and <4 x i32> %astype.i.i.74.i, undef + %or.i.i.79.i = or <4 x i32> %and.i.i.76.i, undef + %astype5.i.i.80.i = bitcast <4 x i32> %or.i.i.79.i to <4 x float> + %1 = shufflevector <4 x float> %astype5.i.i.80.i, <4 x float> undef, <8 x i32> + %2 = shufflevector <8 x float> undef, <8 x float> %1, <8 x i32> + store <8 x float> %2, <8 x float>* undef, align 32 + br label %if.end + +; CHECK-LABEL: @acosh_float8 +; CHECK: xvmaddasp + +if.end: ; preds = %if.then, %entry + ret void +} + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } + -- 2.34.1