From 420c69da57f4c90859dbb51ece63bf5be16ffc82 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 15 Mar 2010 05:53:47 +0000 Subject: [PATCH] do some serious surgery on CellSPU to get it back into a world where it uses types consistently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98532 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/CellSPU/CellSDKIntrinsics.td | 8 ++-- lib/Target/CellSPU/SPU64InstrInfo.td | 9 ++-- lib/Target/CellSPU/SPUInstrInfo.td | 60 ++++++++++++------------- lib/Target/CellSPU/SPUOperands.td | 11 +++++ 4 files changed, 50 insertions(+), 38 deletions(-) diff --git a/lib/Target/CellSPU/CellSDKIntrinsics.td b/lib/Target/CellSPU/CellSDKIntrinsics.td index 1fe7aff94a7..9468aee067a 100644 --- a/lib/Target/CellSPU/CellSDKIntrinsics.td +++ b/lib/Target/CellSPU/CellSDKIntrinsics.td @@ -205,10 +205,9 @@ def CellSDKnand: // Shift/rotate intrinsics: //===----------------------------------------------------------------------===// -/* FIXME: These have (currently unenforced) type conflicts. */ def CellSDKshli: Pat<(int_spu_si_shli (v4i32 VECREG:$rA), uimm7:$val), - (SHLIv4i32 VECREG:$rA, uimm7:$val)>; + (SHLIv4i32 VECREG:$rA, (TO_IMM32 imm:$val))>; def CellSDKshlqbi: Pat<(int_spu_si_shlqbi VECREG:$rA, R32C:$rB), @@ -216,7 +215,7 @@ def CellSDKshlqbi: def CellSDKshlqii: Pat<(int_spu_si_shlqbii VECREG:$rA, uimm7:$val), - (SHLQBIIv16i8 VECREG:$rA, uimm7:$val)>; + (SHLQBIIv16i8 VECREG:$rA, (TO_IMM32 imm:$val))>; def CellSDKshlqby: Pat<(int_spu_si_shlqby VECREG:$rA, R32C:$rB), @@ -224,7 +223,8 @@ def CellSDKshlqby: def CellSDKshlqbyi: Pat<(int_spu_si_shlqbyi VECREG:$rA, uimm7:$val), - (SHLQBYIv16i8 VECREG:$rA, uimm7:$val)>; + (SHLQBYIv16i8 VECREG:$rA, (TO_IMM32 imm:$val))>; + //===----------------------------------------------------------------------===// // Branch/compare intrinsics: diff --git a/lib/Target/CellSPU/SPU64InstrInfo.td b/lib/Target/CellSPU/SPU64InstrInfo.td index 47cb579d9de..069a182c26d 100644 --- a/lib/Target/CellSPU/SPU64InstrInfo.td +++ b/lib/Target/CellSPU/SPU64InstrInfo.td @@ -155,8 +155,9 @@ multiclass CompareLogicalGreaterEqual64 { defm I64LGE: CompareLogicalGreaterEqual64; def : Pat<(setuge R64C:$rA, R64C:$rB), I64LGEr64.Fragment>; -def : Pat<(setuge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), - I64LGEv2i64.Fragment>; +def : Pat<(v2i64 (setuge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB))), + I64LGEv2i64.Fragment>; + // i64 setult: def : I64SETCCNegCond; @@ -233,8 +234,8 @@ multiclass CompareGreaterEqual64 { defm I64GE: CompareGreaterEqual64; def : Pat<(setge R64C:$rA, R64C:$rB), I64GEr64.Fragment>; -def : Pat<(setge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), - I64GEv2i64.Fragment>; +def : Pat<(v2i64 (setge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB))), + I64GEv2i64.Fragment>; // i64 setult: def : I64SETCCNegCond; diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index b96b64ecd06..ad12604faa1 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -2179,10 +2179,10 @@ multiclass ShiftLeftHalfwordImm defm SHLHI : ShiftLeftHalfwordImm; def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)), - (SHLHIv8i16 VECREG:$rA, uimm7:$val)>; + (SHLHIv8i16 VECREG:$rA, (TO_IMM16 uimm7:$val))>; def : Pat<(shl R16C:$rA, (i32 uimm7:$val)), - (SHLHIr16 R16C:$rA, uimm7:$val)>; + (SHLHIr16 R16C:$rA, (TO_IMM16 uimm7:$val))>; //===----------------------------------------------------------------------===// @@ -2410,8 +2410,8 @@ multiclass RotateLeftHalfwordImm defm ROTHI: RotateLeftHalfwordImm; -def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)), - (ROTHIv8i16 VECREG:$rA, imm:$val)>; +def : Pat<(SPUvec_rotl (v8i16 VECREG:$rA), (i32 uimm7:$val)), + (ROTHIv8i16 VECREG:$rA, (TO_IMM16 imm:$val))>; //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // Rotate word: @@ -2682,10 +2682,10 @@ def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)), (ROTHMIv8i16 VECREG:$rA, imm:$val)>; def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)), - (ROTHMIv8i16 VECREG:$rA, imm:$val)>; + (ROTHMIv8i16 VECREG:$rA, (TO_IMM32 imm:$val))>; def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)), - (ROTHMIv8i16 VECREG:$rA, imm:$val)>; + (ROTHMIv8i16 VECREG:$rA, (TO_IMM32 imm:$val))>; def ROTHMIr16: ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val), @@ -2695,10 +2695,10 @@ def: Pat<(srl R16C:$rA, (i32 uimm7:$val)), (ROTHMIr16 R16C:$rA, uimm7:$val)>; def: Pat<(srl R16C:$rA, (i16 uimm7:$val)), - (ROTHMIr16 R16C:$rA, uimm7:$val)>; + (ROTHMIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>; def: Pat<(srl R16C:$rA, (i8 uimm7:$val)), - (ROTHMIr16 R16C:$rA, uimm7:$val)>; + (ROTHMIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>; // ROTM v4i32 form: See the ROTHM v8i16 comments. class ROTMInst pattern>: @@ -2709,14 +2709,14 @@ def ROTMv4i32: ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), [/* see patterns below - $rB must be negated */]>; -def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB), +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R32C:$rB), (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>; -def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB), +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R16C:$rB), (ROTMv4i32 VECREG:$rA, (SFIr32 (XSHWr16 R16C:$rB), 0))>; -def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB), +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R8C:$rB), (ROTMv4i32 VECREG:$rA, (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>; @@ -2742,11 +2742,11 @@ def ROTMIv4i32: [(set (v4i32 VECREG:$rT), (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>; -def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)), - (ROTMIv4i32 VECREG:$rA, uimm7:$val)>; +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (i16 uimm7:$val)), + (ROTMIv4i32 VECREG:$rA, (TO_IMM32 uimm7:$val))>; -def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)), - (ROTMIv4i32 VECREG:$rA, uimm7:$val)>; +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (i8 uimm7:$val)), + (ROTMIv4i32 VECREG:$rA, (TO_IMM32 uimm7:$val))>; // ROTMI r32 form: know how to complement the immediate value. def ROTMIr32: @@ -2755,10 +2755,10 @@ def ROTMIr32: [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>; def : Pat<(srl R32C:$rA, (i16 imm:$val)), - (ROTMIr32 R32C:$rA, uimm7:$val)>; + (ROTMIr32 R32C:$rA, (TO_IMM32 uimm7:$val))>; def : Pat<(srl R32C:$rA, (i8 imm:$val)), - (ROTMIr32 R32C:$rA, uimm7:$val)>; + (ROTMIr32 R32C:$rA, (TO_IMM32 uimm7:$val))>; //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // ROTQMBY: This is a vector form merely so that when used in an @@ -2916,14 +2916,14 @@ def ROTMAHv8i16: "rotmah\t$rT, $rA, $rB", RotateShift, [/* see patterns below - $rB must be negated */]>; -def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB), +def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R32C:$rB), (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>; -def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB), +def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R16C:$rB), (ROTMAHv8i16 VECREG:$rA, (SFIr32 (XSHWr16 R16C:$rB), 0))>; -def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB), +def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R8C:$rB), (ROTMAHv8i16 VECREG:$rA, (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>; @@ -2950,10 +2950,10 @@ def ROTMAHIv8i16: (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>; def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)), - (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>; + (ROTMAHIv8i16 (v8i16 VECREG:$rA), (TO_IMM32 uimm7:$val))>; def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)), - (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>; + (ROTMAHIv8i16 (v8i16 VECREG:$rA), (TO_IMM32 uimm7:$val))>; def ROTMAHIr16: RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val), @@ -2961,25 +2961,25 @@ def ROTMAHIr16: [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>; def : Pat<(sra R16C:$rA, (i32 imm:$val)), - (ROTMAHIr16 R16C:$rA, uimm7:$val)>; + (ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>; def : Pat<(sra R16C:$rA, (i8 imm:$val)), - (ROTMAHIr16 R16C:$rA, uimm7:$val)>; + (ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>; def ROTMAv4i32: RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), "rotma\t$rT, $rA, $rB", RotateShift, [/* see patterns below - $rB must be negated */]>; -def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB), - (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>; +def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R32C:$rB), + (ROTMAv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>; -def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB), - (ROTMAv4i32 (v4i32 VECREG:$rA), +def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R16C:$rB), + (ROTMAv4i32 VECREG:$rA, (SFIr32 (XSHWr16 R16C:$rB), 0))>; -def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB), - (ROTMAv4i32 (v4i32 VECREG:$rA), +def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R8C:$rB), + (ROTMAv4i32 VECREG:$rA, (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>; def ROTMAr32: diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td index 802628f8996..6216651e48a 100644 --- a/lib/Target/CellSPU/SPUOperands.td +++ b/lib/Target/CellSPU/SPUOperands.td @@ -9,6 +9,17 @@ // Cell SPU Instruction Operands: //===----------------------------------------------------------------------===// +// TO_IMM32 - Convert an i8/i16 to i32. +def TO_IMM32 : SDNodeXFormgetZExtValue()); +}]>; + +// TO_IMM16 - Convert an i8/i32 to i16. +def TO_IMM16 : SDNodeXFormgetTargetConstant(N->getZExtValue(), MVT::i16); +}]>; + + def LO16 : SDNodeXFormgetZExtValue(); // Transformation function: get the low 16 bits. -- 2.34.1