From 324cd41b606d6bff31102457f8e6f355132e06d2 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Wed, 22 Oct 2014 16:49:14 +0000 Subject: [PATCH] [Hexagon] Adding basic disassembler. Marking all instructions as CodeGenOnly since encoding bits are not set yet. http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220393 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/CMakeLists.txt | 20 +-- .../Hexagon/Disassembler/CMakeLists.txt | 3 + .../Disassembler/HexagonDisassembler.cpp | 131 ++++++++++++++++++ lib/Target/Hexagon/Disassembler/LLVMBuild.txt | 23 +++ lib/Target/Hexagon/Disassembler/Makefile | 16 +++ lib/Target/Hexagon/HexagonInstrFormats.td | 19 ++- lib/Target/Hexagon/HexagonInstrInfo.td | 4 +- lib/Target/Hexagon/LLVMBuild.txt | 14 +- .../Hexagon/MCTargetDesc/HexagonBaseInfo.h | 35 +++-- lib/Target/Hexagon/Makefile | 17 +-- 10 files changed, 238 insertions(+), 44 deletions(-) create mode 100644 lib/Target/Hexagon/Disassembler/CMakeLists.txt create mode 100644 lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp create mode 100644 lib/Target/Hexagon/Disassembler/LLVMBuild.txt create mode 100644 lib/Target/Hexagon/Disassembler/Makefile diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt index 3627905a3e6..a7f0f49dcb9 100644 --- a/lib/Target/Hexagon/CMakeLists.txt +++ b/lib/Target/Hexagon/CMakeLists.txt @@ -1,8 +1,9 @@ -set(LLVM_TARGET_DEFINITIONS Hexagon.td) - -tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info) -tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info) -tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter) +set(LLVM_TARGET_DEFINITIONS Hexagon.td) + +tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler) +tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info) +tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info) +tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel) tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv) @@ -38,7 +39,8 @@ add_llvm_target(HexagonCodeGen HexagonCopyToCombine.cpp ) -add_subdirectory(TargetInfo) -add_subdirectory(InstPrinter) -add_subdirectory(MCTargetDesc) - +add_subdirectory(TargetInfo) +add_subdirectory(InstPrinter) +add_subdirectory(MCTargetDesc) +add_subdirectory(Disassembler) + diff --git a/lib/Target/Hexagon/Disassembler/CMakeLists.txt b/lib/Target/Hexagon/Disassembler/CMakeLists.txt new file mode 100644 index 00000000000..98629741572 --- /dev/null +++ b/lib/Target/Hexagon/Disassembler/CMakeLists.txt @@ -0,0 +1,3 @@ +add_llvm_library(LLVMHexagonDisassembler + HexagonDisassembler.cpp + ) diff --git a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp new file mode 100644 index 00000000000..688b8e6287f --- /dev/null +++ b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -0,0 +1,131 @@ +//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/HexagonBaseInfo.h" +#include "MCTargetDesc/HexagonMCTargetDesc.h" + +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/LEB128.h" +#include "llvm/Support/MemoryObject.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/Endian.h" + +#include +#include + +using namespace llvm; + +#define DEBUG_TYPE "hexagon-disassembler" + +using DecodeStatus = MCDisassembler::DecodeStatus; + +namespace { +/// \brief Hexagon disassembler for all Hexagon platforms. +class HexagonDisassembler : public MCDisassembler { +public: + HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx) + : MCDisassembler(STI, Ctx) {} + + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + MemoryObject const ®ion, uint64_t address, + raw_ostream &vStream, raw_ostream &cStream) const override; +}; +} + +static const uint16_t IntRegDecoderTable[] = { + Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, + Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, + Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, + Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, + Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, + Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, + Hexagon::R30, Hexagon::R31}; + +static const uint16_t DoubleRegDecoderTable[] = { + Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, + Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, + Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, + Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; + +static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, + Hexagon::P2, Hexagon::P3}; + +static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + void const *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + + unsigned Register = IntRegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::CreateReg(Register)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + void const *Decoder) { + if (RegNo > 15) + return MCDisassembler::Fail; + + unsigned Register = DoubleRegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::CreateReg(Register)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + void const *Decoder) { + if (RegNo > 3) + return MCDisassembler::Fail; + + unsigned Register = PredRegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::CreateReg(Register)); + return MCDisassembler::Success; +} + +#include "HexagonGenDisassemblerTables.inc" + +static MCDisassembler *createHexagonDisassembler(Target const &T, + MCSubtargetInfo const &STI, + MCContext &Ctx) { + return new HexagonDisassembler(STI, Ctx); +} + +extern "C" void LLVMInitializeHexagonDisassembler() { + TargetRegistry::RegisterMCDisassembler(TheHexagonTarget, + createHexagonDisassembler); +} + +DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, + MemoryObject const &Region, + uint64_t Address, + raw_ostream &os, + raw_ostream &cs) const { + std::array Bytes; + Size = 4; + if (Region.readBytes(Address, Bytes.size(), Bytes.data()) == -1) { + return MCDisassembler::Fail; + } + uint32_t insn = + llvm::support::endian::read(Bytes.data()); + + // Remove parse bits. + insn &= ~static_cast(HexagonII::InstParseBits::INST_PARSE_MASK); + return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); +} diff --git a/lib/Target/Hexagon/Disassembler/LLVMBuild.txt b/lib/Target/Hexagon/Disassembler/LLVMBuild.txt new file mode 100644 index 00000000000..eef09e3569d --- /dev/null +++ b/lib/Target/Hexagon/Disassembler/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===-- ./lib/Target/Hexagon/Disassembler/LLVMBuild.txt ---------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = HexagonDisassembler +parent = Hexagon +required_libraries = HexagonDesc MCDisassembler HexagonInfo Support +add_to_library_groups = Hexagon diff --git a/lib/Target/Hexagon/Disassembler/Makefile b/lib/Target/Hexagon/Disassembler/Makefile new file mode 100644 index 00000000000..e55fd58524a --- /dev/null +++ b/lib/Target/Hexagon/Disassembler/Makefile @@ -0,0 +1,16 @@ +##===-- lib/Target/Hexagon/Disassembler/Makefile -----------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMHexagonDisassembler + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index 10573434932..cc27c4c8ed8 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -92,12 +92,18 @@ class InstHexagon pattern, let AsmString = asmstr; let Pattern = pattern; let Constraints = cstr; - let Itinerary = itin; - let Size = 4; - - // *** Must match MCTargetDesc/HexagonBaseInfo.h *** - - // Instruction type according to the ISA. + let Itinerary = itin; + let Size = 4; + + // SoftFail is a field the disassembler can use to provide a way for + // instructions to not match without killing the whole decode process. It is + // mainly used for ARM, but Tablegen expects this field to exist or it fails + // to build the decode table. + field bits<32> SoftFail = 0; + + // *** Must match MCTargetDesc/HexagonBaseInfo.h *** + + // Instruction type according to the ISA. IType Type = type; let TSFlags{4-0} = Type.Value; @@ -186,6 +192,7 @@ class InstHexagon pattern, ""); let PNewValue = !if(isPredicatedNew, "new", ""); let NValueST = !if(isNVStore, "true", "false"); + let isCodeGenOnly = 1; // *** Must match MCTargetDesc/HexagonBaseInfo.h *** } diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 4dcf101ea3a..42ecab9538a 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -225,7 +225,7 @@ def AND_ri : ALU32_ri<(outs IntRegs:$dst), s10ExtPred:$src2))]>, ImmRegRel; // Nop. -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isCodeGenOnly = 0 in def NOP : ALU32_rr<(outs), (ins), "nop", []>; @@ -753,7 +753,7 @@ def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>; let InputType = "imm", isBarrier = 1, isPredicable = 1, Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1, -opExtentBits = 24 in +opExtentBits = 24, isCodeGenOnly = 0 in class T_JMP JumpList = []> : JInst<(outs), InsDag, "jump $dst" , JumpList> { diff --git a/lib/Target/Hexagon/LLVMBuild.txt b/lib/Target/Hexagon/LLVMBuild.txt index a436b6e0454..2cacdca0b30 100644 --- a/lib/Target/Hexagon/LLVMBuild.txt +++ b/lib/Target/Hexagon/LLVMBuild.txt @@ -13,13 +13,13 @@ ; ; http://llvm.org/docs/LLVMBuild.html ; -;===------------------------------------------------------------------------===; - -[common] -subdirectories = InstPrinter MCTargetDesc TargetInfo - -[component_0] -type = TargetGroup +;===------------------------------------------------------------------------===; + +[common] +subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo + +[component_0] +type = TargetGroup name = Hexagon parent = Target has_asmprinter = 1 diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 01044f0fa8c..c8e2d965ccf 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -17,12 +17,14 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H -#include "HexagonMCTargetDesc.h" -#include "llvm/Support/ErrorHandling.h" - -namespace llvm { - -/// HexagonII - This namespace holds all of the target specific flags that +#include "HexagonMCTargetDesc.h" +#include "llvm/Support/ErrorHandling.h" + +#include + +namespace llvm { + +/// HexagonII - This namespace holds all of the target specific flags that /// instruction info tracks. /// namespace HexagonII { @@ -186,11 +188,20 @@ namespace HexagonII { MO_LO16, MO_HI16, // Offset from the base of the SDA. - MO_GPREL - }; - -} // End namespace HexagonII. - -} // End namespace llvm. + MO_GPREL + }; + + enum class InstParseBits : uint32_t { + INST_PARSE_MASK = 0x0000c000, + INST_PARSE_PACKET_END = 0x0000c000, + INST_PARSE_LOOP_END = 0x00008000, + INST_PARSE_NOT_END = 0x00004000, + INST_PARSE_DUPLEX = 0x00000000, + INST_PARSE_EXTENDER = 0x00000000 + }; + +} // End namespace HexagonII. + +} // End namespace llvm. #endif diff --git a/lib/Target/Hexagon/Makefile b/lib/Target/Hexagon/Makefile index d4c93ca8731..ccc0bbac588 100644 --- a/lib/Target/Hexagon/Makefile +++ b/lib/Target/Hexagon/Makefile @@ -14,11 +14,12 @@ TARGET = Hexagon BUILT_SOURCES = HexagonGenRegisterInfo.inc \ HexagonGenInstrInfo.inc \ HexagonGenAsmWriter.inc \ - HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \ - HexagonGenCallingConv.inc \ - HexagonGenDFAPacketizer.inc \ - HexagonGenMCCodeEmitter.inc - -DIRS = InstPrinter TargetInfo MCTargetDesc - -include $(LEVEL)/Makefile.common + HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \ + HexagonGenCallingConv.inc \ + HexagonGenDFAPacketizer.inc \ + HexagonGenMCCodeEmitter.inc \ + HexagonGenDisassemblerTables.inc + +DIRS = InstPrinter TargetInfo MCTargetDesc Disassembler + +include $(LEVEL)/Makefile.common -- 2.34.1