From 31c9cd065a98b82f1dda5461eec0d35ae1f87b09 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Thu, 9 Oct 2014 00:57:31 +0000 Subject: [PATCH] Remove uses of the TargetMachine from FunctionLoweringInfo via caching TargetLowering and using the MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219375 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/FunctionLoweringInfo.h | 4 +--- .../SelectionDAG/FunctionLoweringInfo.cpp | 24 ++++++++----------- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- 3 files changed, 12 insertions(+), 18 deletions(-) diff --git a/include/llvm/CodeGen/FunctionLoweringInfo.h b/include/llvm/CodeGen/FunctionLoweringInfo.h index e94c10569f3..91f20d03472 100644 --- a/include/llvm/CodeGen/FunctionLoweringInfo.h +++ b/include/llvm/CodeGen/FunctionLoweringInfo.h @@ -51,10 +51,10 @@ class Value; /// function that is used when lowering a region of the function. /// class FunctionLoweringInfo { - const TargetMachine &TM; public: const Function *Fn; MachineFunction *MF; + const TargetLowering *TLI; MachineRegisterInfo *RegInfo; BranchProbabilityInfo *BPI; /// CanLowerReturn - true iff the function's return value can be lowered to @@ -127,8 +127,6 @@ public: /// SelectionDAGISel::PrepareEHLandingPad(). unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg; - explicit FunctionLoweringInfo(const TargetMachine &TM) : TM(TM) {} - /// set - Initialize this FunctionLoweringInfo with the given Function /// and its associated MachineFunction. /// diff --git a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index d1fcbe54f26..ff1cfe2d32b 100644 --- a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -80,18 +80,16 @@ static ISD::NodeType getPreferredExtendForValue(const Value *V) { void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, SelectionDAG *DAG) { - const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering(); - Fn = &fn; MF = &mf; + TLI = MF->getSubtarget().getTargetLowering(); RegInfo = &MF->getRegInfo(); // Check whether the function can return without sret-demotion. SmallVector Outs; GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI); CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF, - Fn->isVarArg(), - Outs, Fn->getContext()); + Fn->isVarArg(), Outs, Fn->getContext()); // Initialize the mapping of values to registers. This is only set up for // instruction values that are used outside of the block that defines @@ -107,8 +105,8 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, Type *Ty = AI->getAllocatedType(); uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty); unsigned Align = - std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty), - AI->getAlignment()); + std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty), + AI->getAlignment()); TySize *= CUI->getZExtValue(); // Get total allocated size. if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. @@ -122,7 +120,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, AI->getAllocatedType()), AI->getAlignment()); unsigned StackAlign = - TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment(); + MF->getSubtarget().getFrameLowering()->getStackAlignment(); if (Align <= StackAlign) Align = 0; // Inform the Frame Information that we have variable-sized objects. @@ -142,9 +140,9 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, if (Op.Type == InlineAsm::isClobber) { // Clobbers don't have SDValue operands, hence SDValue(). TLI->ComputeConstraintToUse(Op, SDValue(), DAG); - std::pair PhysReg = - TLI->getRegForInlineAsmConstraint(Op.ConstraintCode, - Op.ConstraintVT); + std::pair PhysReg = + TLI->getRegForInlineAsmConstraint(Op.ConstraintCode, + Op.ConstraintVT); if (PhysReg.first == SP) MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true); } @@ -281,7 +279,7 @@ void FunctionLoweringInfo::clear() { /// CreateReg - Allocate a single virtual register for the given type. unsigned FunctionLoweringInfo::CreateReg(MVT VT) { return RegInfo->createVirtualRegister( - TM.getSubtargetImpl()->getTargetLowering()->getRegClassFor(VT)); + MF->getSubtarget().getTargetLowering()->getRegClassFor(VT)); } /// CreateRegs - Allocate the appropriate number of virtual registers of @@ -292,7 +290,7 @@ unsigned FunctionLoweringInfo::CreateReg(MVT VT) { /// will assign registers for each member or element. /// unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) { - const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering(); + const TargetLowering *TLI = MF->getSubtarget().getTargetLowering(); SmallVector ValueVTs; ComputeValueVTs(*TLI, Ty, ValueVTs); @@ -341,8 +339,6 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) { if (!Ty->isIntegerTy() || Ty->isVectorTy()) return; - const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering(); - SmallVector ValueVTs; ComputeValueVTs(*TLI, Ty, ValueVTs); assert(ValueVTs.size() == 1 && diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 006f3e0143a..a610e571810 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -336,7 +336,7 @@ void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : MachineFunctionPass(ID), TM(tm), - FuncInfo(new FunctionLoweringInfo(TM)), + FuncInfo(new FunctionLoweringInfo()), CurDAG(new SelectionDAG(tm, OL)), SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), GFI(), -- 2.34.1