From 30e21e7109a6467f2c5e60521c5ec849f6aededb Mon Sep 17 00:00:00 2001
From: Matthew Simpson <mssimpso@codeaurora.org>
Date: Thu, 17 Dec 2015 21:29:47 +0000
Subject: [PATCH] Revert "[AArch64] Add DAG combine for extract extend pattern"

This reverts commit r255895. The patch breaks internal tests. Reverting until a
fix is ready.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255928 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AArch64/AArch64ISelLowering.cpp | 20 +-------------------
 test/CodeGen/AArch64/arm64-neon-copy.ll    | 17 +++++++++--------
 2 files changed, 10 insertions(+), 27 deletions(-)

diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index 2ede39eb7f2..9f5beff1210 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8450,25 +8450,6 @@ static SDValue performExtendCombine(SDNode *N,
     }
   }
 
-  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-
-  // If we see (any_extend (extract_vector_element v, i)), we can potentially
-  // remove the extend and promote the extract. We can do this if the vector
-  // type is legal and if the result is sign extended from the element type.
-  if (DCI.isAfterLegalizeVectorOps() && N->getOpcode() == ISD::ANY_EXTEND &&
-      N->hasOneUse() && N->use_begin()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
-    const SDValue &M = N->getOperand(0);
-    if (M.getNode()->hasOneUse() && M.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
-      EVT DstTy = N->getValueType(0);
-      EVT SrcTy = cast<VTSDNode>(N->use_begin()->getOperand(1))->getVT();
-      EVT VecTy = M.getOperand(0).getValueType();
-      EVT ElmTy = VecTy.getScalarType();
-      if (TLI.isTypeLegal(VecTy) && SrcTy == ElmTy)
-        return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), DstTy,
-                           M.getOperand(0), M.getOperand(1));
-    }
-  }
-
   // This is effectively a custom type legalization for AArch64.
   //
   // Type legalization will split an extend of a small, legal, type to a larger
@@ -8499,6 +8480,7 @@ static SDValue performExtendCombine(SDNode *N,
   // We're only interested in cleaning things up for non-legal vector types
   // here. If both the source and destination are legal, things will just
   // work naturally without any fiddling.
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   EVT ResVT = N->getValueType(0);
   if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
     return SDValue();
diff --git a/test/CodeGen/AArch64/arm64-neon-copy.ll b/test/CodeGen/AArch64/arm64-neon-copy.ll
index 83b1cac70f5..b74a40626ce 100644
--- a/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -320,20 +320,21 @@ define i32 @smovw8h(<8 x i16> %tmp1) {
   ret i32 %tmp5
 }
 
-define i64 @smovx16b(<16 x i8> %tmp1) {
+define i32 @smovx16b(<16 x i8> %tmp1) {
 ; CHECK-LABEL: smovx16b:
-; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[8]
+; CHECK: smov {{[xw][0-9]+}}, {{v[0-9]+}}.b[8]
   %tmp3 = extractelement <16 x i8> %tmp1, i32 8
-  %tmp4 = sext i8 %tmp3 to i64
-  ret i64 %tmp4
+  %tmp4 = sext i8 %tmp3 to i32
+  %tmp5 = add i32 %tmp4, %tmp4
+  ret i32 %tmp5
 }
 
-define i64 @smovx8h(<8 x i16> %tmp1) {
+define i32 @smovx8h(<8 x i16> %tmp1) {
 ; CHECK-LABEL: smovx8h:
-; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]
+; CHECK: smov {{[xw][0-9]+}}, {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <8 x i16> %tmp1, i32 2
-  %tmp4 = sext i16 %tmp3 to i64
-  ret i64 %tmp4
+  %tmp4 = sext i16 %tmp3 to i32
+  ret i32 %tmp4
 }
 
 define i64 @smovx4s(<4 x i32> %tmp1) {
-- 
2.34.1