From 30b2a19f3be840da1bc4aefcaabcbddd2e0130fc Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Mon, 11 Nov 2013 18:04:07 +0000 Subject: [PATCH] [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/IntrinsicsAArch64.td | 12 ++++ lib/Target/AArch64/AArch64InstrNEON.td | 28 +++++++- test/CodeGen/AArch64/neon-scalar-cvt.ll | 64 ++++++++++++++++--- test/MC/AArch64/neon-diagnostics.s | 36 +++++++++++ test/MC/AArch64/neon-scalar-cvt.s | 20 ++++++ .../AArch64/neon-instructions.txt | 16 +++++ 6 files changed, 165 insertions(+), 11 deletions(-) diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td index b66bdcc01c3..0bff9876e4f 100644 --- a/include/llvm/IR/IntrinsicsAArch64.td +++ b/include/llvm/IR/IntrinsicsAArch64.td @@ -272,6 +272,18 @@ def int_aarch64_neon_vcvtf32_n_u32 : def int_aarch64_neon_vcvtf64_n_u64 : Intrinsic<[llvm_v1f64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; +// Scalar Floating-point Convert To Signed Fixed-point (Immediate) +def int_aarch64_neon_vcvts_n_s32_f32 : + Intrinsic<[llvm_v1i32_ty], [llvm_v1f32_ty, llvm_i32_ty], [IntrNoMem]>; +def int_aarch64_neon_vcvtd_n_s64_f64 : + Intrinsic<[llvm_v1i64_ty], [llvm_v1f64_ty, llvm_i32_ty], [IntrNoMem]>; + +// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate) +def int_aarch64_neon_vcvts_n_u32_f32 : + Intrinsic<[llvm_v1i32_ty], [llvm_v1f32_ty, llvm_i32_ty], [IntrNoMem]>; +def int_aarch64_neon_vcvtd_n_u64_f64 : + Intrinsic<[llvm_v1i64_ty], [llvm_v1f64_ty, llvm_i32_ty], [IntrNoMem]>; + class Neon_SHA_Intrinsic : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v1i32_ty, llvm_v4i32_ty], [IntrNoMem]>; diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 5cdac1ef884..c53909edce6 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -4058,7 +4058,7 @@ multiclass NeonI_ScalarShiftImm_narrow_HSD_size opcode, } } -multiclass NeonI_ScalarShiftImm_scvtf_SD_size opcode, string asmop> { +multiclass NeonI_ScalarShiftImm_cvt_SD_size opcode, string asmop> { def ssi : NeonI_ScalarShiftImm_size { bits<5> Imm; let Inst{22-21} = 0b01; // immh:immb = 01xxxxx @@ -4119,6 +4119,16 @@ multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns; } +multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns { + def ssi : Pat<(v1i32 (Sopnode (v1f32 FPR32:$Rn), (i32 imm:$Imm))), + (INSTS FPR32:$Rn, imm:$Imm)>; + def ddi : Pat<(v1i64 (Dopnode (v1f64 FPR64:$Rn), (i32 imm:$Imm))), + (INSTD FPR64:$Rn, imm:$Imm)>; +} + // Scalar Signed Shift Right (Immediate) defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">; defm : Neon_ScalarShiftImm_D_size_patterns; @@ -4218,17 +4228,29 @@ defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns; // Scalar Signed Fixed-point Convert To Floating-Point (Immediate) -defm SCVTF_N : NeonI_ScalarShiftImm_scvtf_SD_size<0b0, 0b11100, "scvtf">; +defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">; defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns; // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate) -defm UCVTF_N : NeonI_ScalarShiftImm_scvtf_SD_size<0b1, 0b11100, "ucvtf">; +defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">; defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns; +// Scalar Floating-point Convert To Signed Fixed-point (Immediate) +defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">; +defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns; + +// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate) +defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">; +defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns; + // Scalar Integer Add let isCommutable = 1 in { def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">; diff --git a/test/CodeGen/AArch64/neon-scalar-cvt.ll b/test/CodeGen/AArch64/neon-scalar-cvt.ll index 056504a67e8..a7f0ac09658 100644 --- a/test/CodeGen/AArch64/neon-scalar-cvt.ll +++ b/test/CodeGen/AArch64/neon-scalar-cvt.ll @@ -5,7 +5,7 @@ define float @test_vcvts_f32_s32(i32 %a) { ; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}} entry: %vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0 - %vcvtf1.i = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.s32(<1 x i32> %vcvtf.i) + %vcvtf1.i = call <1 x float> @llvm.aarch64.neon.vcvtf32.s32(<1 x i32> %vcvtf.i) %0 = extractelement <1 x float> %vcvtf1.i, i32 0 ret float %0 } @@ -17,7 +17,7 @@ define double @test_vcvtd_f64_s64(i64 %a) { ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}} entry: %vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0 - %vcvtf1.i = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.s64(<1 x i64> %vcvtf.i) + %vcvtf1.i = call <1 x double> @llvm.aarch64.neon.vcvtf64.s64(<1 x i64> %vcvtf.i) %0 = extractelement <1 x double> %vcvtf1.i, i32 0 ret double %0 } @@ -29,7 +29,7 @@ define float @test_vcvts_f32_u32(i32 %a) { ; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}} entry: %vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0 - %vcvtf1.i = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.u32(<1 x i32> %vcvtf.i) + %vcvtf1.i = call <1 x float> @llvm.aarch64.neon.vcvtf32.u32(<1 x i32> %vcvtf.i) %0 = extractelement <1 x float> %vcvtf1.i, i32 0 ret float %0 } @@ -41,7 +41,7 @@ define double @test_vcvtd_f64_u64(i64 %a) { ; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}} entry: %vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0 - %vcvtf1.i = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.u64(<1 x i64> %vcvtf.i) + %vcvtf1.i = call <1 x double> @llvm.aarch64.neon.vcvtf64.u64(<1 x i64> %vcvtf.i) %0 = extractelement <1 x double> %vcvtf1.i, i32 0 ret double %0 } @@ -53,7 +53,7 @@ define float @test_vcvts_n_f32_s32(i32 %a) { ; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}, #1 entry: %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0 - %vcvtf1 = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32> %vcvtf, i32 1) + %vcvtf1 = call <1 x float> @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32> %vcvtf, i32 1) %0 = extractelement <1 x float> %vcvtf1, i32 0 ret float %0 } @@ -65,7 +65,7 @@ define double @test_vcvtd_n_f64_s64(i64 %a) { ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}, #1 entry: %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0 - %vcvtf1 = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64> %vcvtf, i32 1) + %vcvtf1 = call <1 x double> @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64> %vcvtf, i32 1) %0 = extractelement <1 x double> %vcvtf1, i32 0 ret double %0 } @@ -77,7 +77,7 @@ define float @test_vcvts_n_f32_u32(i32 %a) { ; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}, #1 entry: %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0 - %vcvtf1 = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32> %vcvtf, i32 1) + %vcvtf1 = call <1 x float> @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32> %vcvtf, i32 1) %0 = extractelement <1 x float> %vcvtf1, i32 0 ret float %0 } @@ -89,9 +89,57 @@ define double @test_vcvtd_n_f64_u64(i64 %a) { ; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}, #1 entry: %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0 - %vcvtf1 = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64> %vcvtf, i32 1) + %vcvtf1 = call <1 x double> @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64> %vcvtf, i32 1) %0 = extractelement <1 x double> %vcvtf1, i32 0 ret double %0 } declare <1 x double> @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64>, i32) + +define i32 @test_vcvts_n_s32_f32(float %a) { +; CHECK: test_vcvts_n_s32_f32 +; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #0 +entry: + %fcvtzs = insertelement <1 x float> undef, float %a, i32 0 + %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float> %fcvtzs, i32 0) + %0 = extractelement <1 x i32> %fcvtzs1, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float>, i32) + +define i64 @test_vcvtd_n_s64_f64(double %a) { +; CHECK: test_vcvtd_n_s64_f64 +; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #0 +entry: + %fcvtzs = insertelement <1 x double> undef, double %a, i32 0 + %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double> %fcvtzs, i32 0) + %0 = extractelement <1 x i64> %fcvtzs1, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double>, i32) + +define i32 @test_vcvts_n_u32_f32(float %a) { +; CHECK: test_vcvts_n_u32_f32 +; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #0 +entry: + %fcvtzu = insertelement <1 x float> undef, float %a, i32 0 + %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float> %fcvtzu, i32 0) + %0 = extractelement <1 x i32> %fcvtzu1, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float>, i32) + +define i64 @test_vcvtd_n_u64_f64(double %a) { +; CHECK: test_vcvtd_n_u64_f64 +; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #0 +entry: + %fcvtzu = insertelement <1 x double> undef, double %a, i32 0 + %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double> %fcvtzu, i32 0) + %0 = extractelement <1 x i64> %fcvtzu1, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double>, i32) diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index d9afcb1418b..5ada875b13a 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -5089,6 +5089,42 @@ // CHECK-ERROR: ucvtf d21, s14, #64 // CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Fixed-point (Immediate) +//---------------------------------------------------------------------- + + fcvtzs s21, s12, #0 + fcvtzs d21, d12, #65 + fcvtzs s21, d12, #1 + +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: fcvtzs s21, s12, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: fcvtzs d21, d12, #65 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs s21, d12, #1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate) +//---------------------------------------------------------------------- + + fcvtzu s21, s12, #33 + fcvtzu d21, d12, #0 + fcvtzu s21, d12, #1 + +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: fcvtzu s21, s12, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: fcvtzu d21, d12, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu s21, d12, #1 +// CHECK-ERROR: ^ + //---------------------------------------------------------------------- // Scalar Unsigned Saturating Extract Narrow //---------------------------------------------------------------------- diff --git a/test/MC/AArch64/neon-scalar-cvt.s b/test/MC/AArch64/neon-scalar-cvt.s index 93115ad6489..54774097c0b 100644 --- a/test/MC/AArch64/neon-scalar-cvt.s +++ b/test/MC/AArch64/neon-scalar-cvt.s @@ -41,3 +41,23 @@ // CHECK: ucvtf s22, s13, #32 // encoding: [0xb6,0xe5,0x20,0x7f] // CHECK: ucvtf d21, d14, #64 // encoding: [0xd5,0xe5,0x40,0x7f] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Fixed-point (Immediate) +//---------------------------------------------------------------------- + + fcvtzs s21, s12, #1 + fcvtzs d21, d12, #1 + +// CHECK: fcvtzs s21, s12, #1 // encoding: [0x95,0xfd,0x3f,0x5f] +// CHECK: fcvtzs d21, d12, #1 // encoding: [0x95,0xfd,0x7f,0x5f] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate) +//---------------------------------------------------------------------- + + fcvtzu s21, s12, #1 + fcvtzu d21, d12, #1 + +// CHECK: fcvtzu s21, s12, #1 // encoding: [0x95,0xfd,0x3f,0x7f] +// CHECK: fcvtzu d21, d12, #1 // encoding: [0x95,0xfd,0x7f,0x7f] diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index e4aad48f473..2f533758153 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -1972,6 +1972,22 @@ G# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | 0xb6,0xe5,0x20,0x7f 0xd5,0xe5,0x40,0x7f +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Fixed-point (Immediate) +#---------------------------------------------------------------------- +# CHECK: fcvtzs s21, s12, #1 +# CHECK: fcvtzs d21, d12, #1 +0x95,0xfd,0x3f,0x5f +0x95,0xfd,0x7f,0x5f + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Fixed-point (Immediate) +#---------------------------------------------------------------------- +# CHECK: fcvtzu s21, s12, #1 +# CHECK: fcvtzu d21, d12, #1 +0x95,0xfd,0x3f,0x7f +0x95,0xfd,0x7f,0x7f + #---------------------------------------------------------------------- # Vector load/store multiple N-element structure #---------------------------------------------------------------------- -- 2.34.1