From 30709900f394ba33d546b6830eadc7307add3219 Mon Sep 17 00:00:00 2001 From: Hrvoje Varga Date: Mon, 30 Nov 2015 12:58:39 +0000 Subject: [PATCH] [mips][microMIPS] Implement LBUX, LHX, LWX, MAQ_S[A].W.PHL, MAQ_S[A].W.PHR, MFHI, MFLO, MTHI and MTLO instructions Differential Revision: http://reviews.llvm.org/D14436 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254297 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMipsDSPInstrFormats.td | 25 +++++++++++++ lib/Target/Mips/MicroMipsDSPInstrInfo.td | 36 +++++++++++++++++++ lib/Target/Mips/MipsDSPInstrInfo.td | 25 +++++++------ .../Disassembler/Mips/micromips-dsp/valid.txt | 11 ++++++ test/MC/Mips/micromips-dsp/valid.s | 11 ++++++ 5 files changed, 97 insertions(+), 11 deletions(-) diff --git a/lib/Target/Mips/MicroMipsDSPInstrFormats.td b/lib/Target/Mips/MicroMipsDSPInstrFormats.td index d3f9fe31afb..f231d3a5294 100644 --- a/lib/Target/Mips/MicroMipsDSPInstrFormats.td +++ b/lib/Target/Mips/MicroMipsDSPInstrFormats.td @@ -153,3 +153,28 @@ class POOL32A_2RSA5_FMT op> : MMDSPInst { let Inst{15-11} = sa; let Inst{10-0} = op; } + +class POOL32A_1RMEMB0_FMT funct> : MMDSPInst { + bits<5> index; + bits<5> base; + bits<5> rd; + + let Inst{31-26} = 0; + let Inst{25-21} = index; + let Inst{20-16} = base; + let Inst{15-11} = rd; + let Inst{10} = 0b0; + let Inst{9-0} = funct; +} + +class POOL32A_1RAC_FMT funct> : MMDSPInst { + bits<5> rs; + bits<2> ac; + + let Inst{31-26} = 0; + let Inst{25-21} = 0; + let Inst{20-16} = rs; + let Inst{15-14} = ac; + let Inst{13-6} = funct; + let Inst{5-0} = 0b111100; +} diff --git a/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/lib/Target/Mips/MicroMipsDSPInstrInfo.td index f515f380f0d..204a4ec60c5 100644 --- a/lib/Target/Mips/MicroMipsDSPInstrInfo.td +++ b/lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -130,6 +130,17 @@ class PRECRQ_QB_PH_MM_ENC : POOL32A_3RB0_FMT<"precrq.qb.ph", 0b0010101101>; class PRECRQU_S_QB_PH_MM_ENC : POOL32A_3RB0_FMT<"precrqu_s.qb.ph", 0b0101101101>; class PRECRQ_RS_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq_rs.ph.w", 0b0100101101>; +class LBUX_MM_ENC : POOL32A_1RMEMB0_FMT<"lbux", 0b1000100101>; +class LHX_MM_ENC : POOL32A_1RMEMB0_FMT<"lhx", 0b0101100101>; +class LWX_MM_ENC : POOL32A_1RMEMB0_FMT<"lwx", 0b0110100101>; +class MAQ_S_W_PHL_MM_ENC : POOL32A_2RAC_FMT<"maq_s.w.phl", 0b01101001>; +class MAQ_SA_W_PHL_MM_ENC : POOL32A_2RAC_FMT<"maq_sa.w.phl", 0b11101001>; +class MAQ_S_W_PHR_MM_ENC : POOL32A_2RAC_FMT<"maq_s.w.phr", 0b00101001>; +class MAQ_SA_W_PHR_MM_ENC : POOL32A_2RAC_FMT<"maq_sa.w.phr", 0b10101001>; +class MFHI_MM_ENC : POOL32A_1RAC_FMT<"mfhi", 0b00000001>; +class MFLO_MM_ENC : POOL32A_1RAC_FMT<"mflo", 0b01000001>; +class MTHI_MM_ENC : POOL32A_1RAC_FMT<"mthi", 0b10000001>; +class MTLO_MM_ENC : POOL32A_1RAC_FMT<"mthi", 0b11000001>; // Instruction desc. class ABSQ_S_PH_MM_R2_DESC_BASE, Defs<[DSPOutFlag23]>; +class MFHI_MM_DESC_BASE { + dag OutOperandList = (outs GPR32Opnd:$rs); + dag InOperandList = (ins RO:$ac); + string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); + list Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))]; + InstrItinClass Itinerary = itin; +} + +class MFHI_MM_DESC : MFHI_MM_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, + NoItinerary>; +class MFLO_MM_DESC : MFHI_MM_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, + NoItinerary>; + // Instruction defs. // microMIPS DSP Rev 1 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC; @@ -368,6 +393,17 @@ def PRECRQ_PH_W_MM : DspMMRel, PRECRQ_PH_W_MM_ENC, PRECRQ_PH_W_DESC; def PRECRQ_QB_PH_MM : DspMMRel, PRECRQ_QB_PH_MM_ENC, PRECRQ_QB_PH_DESC; def PRECRQU_S_QB_PH_MM : DspMMRel, PRECRQU_S_QB_PH_MM_ENC, PRECRQU_S_QB_PH_DESC; def PRECRQ_RS_PH_W_MM : DspMMRel, PRECRQ_RS_PH_W_MM_ENC, PRECRQ_RS_PH_W_DESC; +def LBUX_MM : DspMMRel, LBUX_MM_ENC, LBUX_DESC; +def LHX_MM : DspMMRel, LHX_MM_ENC, LHX_DESC; +def LWX_MM : DspMMRel, LWX_MM_ENC, LWX_DESC; +def MAQ_S_W_PHL_MM : DspMMRel, MAQ_S_W_PHL_MM_ENC, MAQ_S_W_PHL_DESC; +def MAQ_SA_W_PHL_MM : DspMMRel, MAQ_SA_W_PHL_MM_ENC, MAQ_SA_W_PHL_DESC; +def MAQ_S_W_PHR_MM : DspMMRel, MAQ_S_W_PHR_MM_ENC, MAQ_S_W_PHR_DESC; +def MAQ_SA_W_PHR_MM : DspMMRel, MAQ_SA_W_PHR_MM_ENC, MAQ_SA_W_PHR_DESC; +def MFHI_DSP_MM : DspMMRel, MFHI_MM_ENC, MFHI_MM_DESC; +def MFLO_DSP_MM : DspMMRel, MFLO_MM_ENC, MFLO_MM_DESC; +def MTHI_DSP_MM : DspMMRel, MTHI_MM_ENC, MTHI_DESC; +def MTLO_DSP_MM : DspMMRel, MTLO_MM_ENC, MTLO_DESC; // microMIPS DSP Rev 2 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, ISA_DSPR2; diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index 91513f3f2c6..e8cfbcf572d 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -360,6 +360,7 @@ class LX_DESC_BASE Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))]; InstrItinClass Itinerary = itin; bit mayLoad = 1; + string BaseOpcode = instr_asm; } class ADDUH_QB_DESC_BASE Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))]; InstrItinClass Itinerary = itin; + string BaseOpcode = instr_asm; } class MTHI_DESC_BASE { @@ -494,6 +496,7 @@ class MTHI_DESC_BASE dag InOperandList = (ins GPR32Opnd:$rs); string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); InstrItinClass Itinerary = itin; + string BaseOpcode = instr_asm; } class BPOSGE32_PSEUDO_DESC_BASE : @@ -1143,14 +1146,14 @@ def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC; -def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; -def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; -def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC; -def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC; -def MFHI_DSP : MFHI_ENC, MFHI_DESC; -def MFLO_DSP : MFLO_ENC, MFLO_DESC; -def MTHI_DSP : MTHI_ENC, MTHI_DESC; -def MTLO_DSP : MTLO_ENC, MTLO_DESC; +def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; +def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; +def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC; +def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC; +def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC; +def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC; +def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC; +def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC; def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC; def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC; def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; @@ -1182,9 +1185,9 @@ def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC; def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC; def PICK_QB : PICK_QB_ENC, PICK_QB_DESC; def PICK_PH : PICK_PH_ENC, PICK_PH_DESC; -def LWX : LWX_ENC, LWX_DESC; -def LHX : LHX_ENC, LHX_DESC; -def LBUX : LBUX_ENC, LBUX_DESC; +def LWX : DspMMRel, LWX_ENC, LWX_DESC; +def LHX : DspMMRel, LHX_ENC, LHX_DESC; +def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC; def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC; def INSV : DspMMRel, INSV_ENC, INSV_DESC; def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC; diff --git a/test/MC/Disassembler/Mips/micromips-dsp/valid.txt b/test/MC/Disassembler/Mips/micromips-dsp/valid.txt index 433022c1e62..ceba6a9823b 100644 --- a/test/MC/Disassembler/Mips/micromips-dsp/valid.txt +++ b/test/MC/Disassembler/Mips/micromips-dsp/valid.txt @@ -76,3 +76,14 @@ 0x00 0x62 0x08 0x95 # CHECK: muleu_s.ph.qbl $1, $2, $3 0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3 0x00,0x62,0x09,0x15 # CHECK: mulq_rs.ph $1, $2, $3 +0x00 0x43 0x0a 0x25 # CHECK: lbux $1, $2($3) +0x00 0x43 0x09 0x65 # CHECK: lhx $1, $2($3) +0x00 0x43 0x09 0xa5 # CHECK: lwx $1, $2($3) +0x00 0x62 0x5a 0x7c # CHECK: maq_s.w.phl $ac1, $2, $3 +0x00 0x62 0x7a 0x7c # CHECK: maq_sa.w.phl $ac1, $2, $3 +0x00 0x62 0x4a 0x7c # CHECK: maq_s.w.phr $ac1, $2, $3 +0x00 0x62 0x6a 0x7c # CHECK: maq_sa.w.phr $ac1, $2, $3 +0x00 0x02 0x40 0x7c # CHECK: mfhi $2, $ac1 +0x00 0x01 0x50 0x7c # CHECK: mflo $1, $ac1 +0x00 0x01 0x60 0x7c # CHECK: mthi $1, $ac1 +0x00 0x01 0x70 0x7c # CHECK: mtlo $1, $ac1 diff --git a/test/MC/Mips/micromips-dsp/valid.s b/test/MC/Mips/micromips-dsp/valid.s index 24e4a07365a..f2eae8f6cae 100644 --- a/test/MC/Mips/micromips-dsp/valid.s +++ b/test/MC/Mips/micromips-dsp/valid.s @@ -77,3 +77,14 @@ muleu_s.ph.qbl $1, $2, $3 # CHECK: muleu_s.ph.qbl $1, $2, $3 # encoding: [0x00,0x62,0x08,0x95] muleu_s.ph.qbr $1, $2, $3 # CHECK: muleu_s.ph.qbr $1, $2, $3 # encoding: [0x00,0x62,0x08,0xd5] mulq_rs.ph $1, $2, $3 # CHECK: mulq_rs.ph $1, $2, $3 # encoding: [0x00,0x62,0x09,0x15] + lbux $1, $2($3) # CHECK: lbux $1, $2($3) # encoding: [0x00,0x43,0x0a,0x25] + lhx $1, $2($3) # CHECK: lhx $1, $2($3) # encoding: [0x00,0x43,0x09,0x65] + lwx $1, $2($3) # CHECK: lwx $1, $2($3) # encoding: [0x00,0x43,0x09,0xa5] + maq_s.w.phl $ac1, $2, $3 # CHECK: maq_s.w.phl $ac1, $2, $3 # encoding: [0x00,0x62,0x5a,0x7c] + maq_sa.w.phl $ac1, $2, $3 # CHECK: maq_sa.w.phl $ac1, $2, $3 # encoding: [0x00,0x62,0x7a,0x7c] + maq_s.w.phr $ac1, $2, $3 # CHECK: maq_s.w.phr $ac1, $2, $3 # encoding: [0x00,0x62,0x4a,0x7c] + maq_sa.w.phr $ac1, $2, $3 # CHECK: maq_sa.w.phr $ac1, $2, $3 # encoding: [0x00,0x62,0x6a,0x7c] + mfhi $2, $ac1 # CHECK: mfhi $2, $ac1 # encoding: [0x00,0x02,0x40,0x7c] + mflo $1, $ac1 # CHECK: mflo $1, $ac1 # encoding: [0x00,0x01,0x50,0x7c] + mthi $1, $ac1 # CHECK: mthi $1, $ac1 # encoding: [0x00,0x01,0x60,0x7c] + mtlo $1, $ac1 # CHECK: mtlo $1, $ac1 # encoding: [0x00,0x01,0x70,0x7c] -- 2.34.1