From 244a84ee57cc73509a0e85cc92585cb567d0b72c Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Thu, 5 Jul 2012 23:58:21 +0000 Subject: [PATCH] Mips specific inline asm operand modifier D. Print the second half of a double word operand. The include list was cleaned up a bit as well. Also the test case was modified to test for both big and little patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159787 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsAsmPrinter.cpp | 48 +++++++++++-- test/CodeGen/Mips/inlineasm-operand-code.ll | 75 +++++++++++++++------ 2 files changed, 94 insertions(+), 29 deletions(-) diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp index 14c4b966647..3be0b287d8d 100644 --- a/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/MipsAsmPrinter.cpp @@ -18,24 +18,23 @@ #include "MipsInstrInfo.h" #include "InstPrinter/MipsInstPrinter.h" #include "MCTargetDesc/MipsBaseInfo.h" -#include "llvm/BasicBlock.h" -#include "llvm/DebugInfo.h" -#include "llvm/Instructions.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Twine.h" -#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/BasicBlock.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/InlineAsm.h" #include "llvm/Instructions.h" -#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLoweringObjectFile.h" @@ -334,8 +333,43 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, O << "$0"; return false; } + // This will be shared with other cases in succeeding checkins + case 'D': { + // Second part of a double word register operand + if (OpNum == 0) + return true; + const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); + if (!FlagsOP.isImm()) + return true; + unsigned Flags = FlagsOP.getImm(); + unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); + if (NumVals != 2) { + if (!Subtarget->isGP32bit() && NumVals == 1 && MO.isReg()) { + // In 64 bit mode long longs are always just a single reg + unsigned Reg = MO.getReg(); + O << '$' << MipsInstPrinter::getRegisterName(Reg); + return false; + } + return true; + } + unsigned RegOp; + switch(ExtraCode[0]) { + // This will have other cases in succeeding checkins + case 'D': + RegOp = (!Subtarget->isGP32bit()) ? OpNum : OpNum + 1; + break; + } + if (RegOp >= MI->getNumOperands()) + return true; + const MachineOperand &MO = MI->getOperand(RegOp); + if (!MO.isReg()) + return true; + unsigned Reg = MO.getReg(); + O << '$' << MipsInstPrinter::getRegisterName(Reg); + return false; } - } + } // switch + } // if ExtraCode printOperand(MI, OpNum, O); return false; diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll index d75f7f2f806..8398cb0e38e 100644 --- a/test/CodeGen/Mips/inlineasm-operand-code.ll +++ b/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -1,51 +1,82 @@ ; Positive test for inline register constraints ; -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=LITTLE +; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=BIG +%union.u_tag = type { i64 } +%struct.anon = type { i32, i32 } +@uval = common global %union.u_tag zeroinitializer, align 8 define i32 @main() nounwind { entry: ; X with -3 -;CHECK: #APP -;CHECK: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd -;CHECK: #NO_APP +;LITTLE: #APP +;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd +;LITTLE: #NO_APP tail call i32 asm sideeffect "addi $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) nounwind ; x with -3 -;CHECK: #APP -;CHECK: addi ${{[0-9]+}},${{[0-9]+}},0xfffd -;CHECK: #NO_APP +;LITTLE: #APP +;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},0xfffd +;LITTLE: #NO_APP tail call i32 asm sideeffect "addi $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) nounwind ; d with -3 -;CHECK: #APP -;CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3 -;CHECK: #NO_APP +;LITTLE: #APP +;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},-3 +;LITTLE: #NO_APP tail call i32 asm sideeffect "addi $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) nounwind ; m with -3 -;CHECK: #APP -;CHECK: addi ${{[0-9]+}},${{[0-9]+}},-4 -;CHECK: #NO_APP +;LITTLE: #APP +;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},-4 +;LITTLE: #NO_APP tail call i32 asm sideeffect "addi $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) nounwind ; z with -3 -;CHECK: #APP -;CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3 -;CHECK: #NO_APP +;LITTLE: #APP +;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},-3 +;LITTLE: #NO_APP tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) nounwind ; z with 0 -;CHECK: #APP -;CHECK: addi ${{[0-9]+}},${{[0-9]+}},$0 -;CHECK: #NO_APP +;LITTLE: #APP +;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},$0 +;LITTLE: #NO_APP tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind ; a long long in 32 bit mode (use to assert) -;CHECK: #APP -;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 -;CHECK: #NO_APP +;LITTLE: #APP +;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},3 +;LITTLE: #NO_APP tail call i64 asm sideeffect "addi $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind +; D, in little endian the source reg will be 4 bytes into the long long +;LITTLE: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +;LITTLE: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +;LITTLE-NEXT: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +;LITTLE: #APP +;LITTLE: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} +;LITTLE: #NO_APP + +; D, in big endian the source reg will also be 4 bytes into the long long +;BIG: #APP +;BIG: #APP +;BIG: #APP +;BIG: #APP +;BIG: #APP +;BIG: #APP +;BIG: #APP +;BIG: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +;BIG: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +;BIG-NEXT: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +;BIG: #APP +;BIG: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} +;BIG: #NO_APP + %7 = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8 + %trunc1 = trunc i64 %7 to i32 + tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %7, i32 %trunc1) nounwind + ret i32 0 } + -- 2.34.1