From 1cc6333161be8bbeb516bc7c74d4400dca58b997 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Wed, 11 Apr 2012 22:59:08 +0000 Subject: [PATCH] Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user, otherwise expand FNEG during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.cpp | 5 +++++ lib/Target/Mips/MipsInstrFPU.td | 7 ++++--- test/CodeGen/Mips/fneg.ll | 17 +++++++++++++++++ 3 files changed, 26 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/Mips/fneg.ll diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 842988c816f..6a23bc3d1d7 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -216,6 +216,11 @@ MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::FREM, MVT::f32, Expand); setOperationAction(ISD::FREM, MVT::f64, Expand); + if (!TM.Options.NoNaNsFPMath) { + setOperationAction(ISD::FNEG, MVT::f32, Expand); + setOperationAction(ISD::FNEG, MVT::f64, Expand); + } + setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 332bc116c02..b6559452fec 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -190,9 +190,10 @@ let Predicates = [IsFP64bit] in { def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>; } -let Predicates = [NoNaNsFPMath] in -defm FABS : FFR1P_M<0x5, "abs", fabs>; -defm FNEG : FFR1P_M<0x7, "neg", fneg>; +let Predicates = [NoNaNsFPMath] in { + defm FABS : FFR1P_M<0x5, "abs", fabs>; + defm FNEG : FFR1P_M<0x7, "neg", fneg>; +} defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>; // The odd-numbered registers are only referenced when doing loads, diff --git a/test/CodeGen/Mips/fneg.ll b/test/CodeGen/Mips/fneg.ll new file mode 100644 index 00000000000..162146f1831 --- /dev/null +++ b/test/CodeGen/Mips/fneg.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s + +define float @foo0(i32 %a, float %d) nounwind readnone { +entry: +; CHECK-NOT: fabs.s + %sub = fsub float -0.000000e+00, %d + ret float %sub +} + +define double @foo1(i32 %a, double %d) nounwind readnone { +entry: +; CHECK: foo1 +; CHECK-NOT: fabs.d +; CHECK: jr + %sub = fsub double -0.000000e+00, %d + ret double %sub +} -- 2.34.1