From 1c140c48ae1ef861e6f49b85fd7941a4e617fc57 Mon Sep 17 00:00:00 2001
From: Daniel Sanders <daniel.sanders@imgtec.com>
Date: Tue, 12 Jan 2016 15:15:14 +0000
Subject: [PATCH] [mips] Correct operand order in DSP's mthi/mtlo

Summary: The result register is the second operand as per the other mt* instructions.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D15993

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257478 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/MipsSEInstrInfo.cpp |  5 +++--
 test/CodeGen/Mips/madd-msub.ll      | 14 +++++++-------
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp
index e6f7fe9aae1..d4aeaf92865 100644
--- a/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -544,8 +544,6 @@ void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
   const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
   MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
   MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
-  LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
-  HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
 
   // Add lo/hi registers if the mtlo/hi instructions created have explicit
   // def registers.
@@ -556,6 +554,9 @@ void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
     LoInst.addReg(DstLo, RegState::Define);
     HiInst.addReg(DstHi, RegState::Define);
   }
+
+  LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
+  HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
 }
 
 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll
index b84d94d3149..667676de5f3 100644
--- a/test/CodeGen/Mips/madd-msub.ll
+++ b/test/CodeGen/Mips/madd-msub.ll
@@ -18,7 +18,7 @@
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       sra $[[T0:[0-9]+]], $6, 31
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       madd $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
@@ -64,7 +64,7 @@ entry:
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       addiu $[[T0:[0-9]+]], $zero, 0
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       maddu $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
@@ -101,8 +101,8 @@ entry:
 ; 32-DAG:        [[m]]fhi $2
 ; 32-DAG:        [[m]]flo $3
 
-; DSP-DAG:       mthi $[[AC:ac[0-3]+]], $6
-; DSP-DAG:       mtlo $[[AC]], $7
+; DSP-DAG:       mthi $6, $[[AC:ac[0-3]+]]
+; DSP-DAG:       mtlo $7, $[[AC]]
 ; DSP-DAG:       madd $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
@@ -143,7 +143,7 @@ entry:
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       sra $[[T0:[0-9]+]], $6, 31
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       msub $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
@@ -189,7 +189,7 @@ entry:
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       addiu $[[T0:[0-9]+]], $zero, 0
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       msubu $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
@@ -229,7 +229,7 @@ entry:
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       addiu $[[T0:[0-9]+]], $zero, 0
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       msub $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
-- 
2.34.1