From 154c41dbbc06284efd56782a8bc137a25148918e Mon Sep 17 00:00:00 2001
From: Owen Anderson <resistor@mac.com>
Date: Thu, 4 Aug 2011 18:24:14 +0000
Subject: [PATCH] LDCL_POST and STCL_POST need one's-complement offsets, rather
 than two's complement offsets.  Add an appropriate immediate type for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrInfo.td                | 13 ++++++++++++-
 lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp |  9 +++++++++
 lib/Target/ARM/InstPrinter/ARMInstPrinter.h   |  2 ++
 utils/TableGen/EDEmitter.cpp                  |  1 +
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index f03aced9cb7..9fac575c1db 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -626,6 +626,17 @@ def postidx_imm8 : Operand<i32> {
   let MIOperandInfo = (ops i32imm);
 }
 
+// postidx_imm8s4 := +/- [0,1020]
+//
+// 9 bit value:
+//  {8}       1 is imm8 is non-negative. 0 otherwise.
+//  {7-0}     [0,255] imm8 value, scaled by 4.
+def postidx_imm8s4 : Operand<i32> {
+  let PrintMethod = "printPostIdxImm8s4Operand";
+  let MIOperandInfo = (ops i32imm);
+}
+
+
 // postidx_reg := +/- reg
 //
 def PostIdxRegAsmOperand : AsmOperandClass {
@@ -3974,7 +3985,7 @@ multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
 
   def L_POST : ACI<(outs),
       !con((ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
-            i32imm:$offset), ops),
+            postidx_imm8s4:$offset), ops),
       !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr, $offset",
       IndexModePost> {
     let Inst{31-28} = op31_28;
diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 2394340e602..37359cec7fa 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -382,6 +382,15 @@ void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
   O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
 }
 
+void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
+                                             unsigned OpNum,
+                                             raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNum);
+  unsigned Imm = MO.getImm();
+  O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
+}
+
+
 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
                                            raw_ostream &O) {
   ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.h b/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
index 9f481e91289..ac78d028359 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
@@ -55,6 +55,8 @@ public:
   void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,raw_ostream &O);
   void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
                                raw_ostream &O);
+  void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
+                               raw_ostream &O);
 
   void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp
index e7dba139844..bf2cbe23c8a 100644
--- a/utils/TableGen/EDEmitter.cpp
+++ b/utils/TableGen/EDEmitter.cpp
@@ -614,6 +614,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
   IMM("shr_imm64");
   IMM("t2ldrlabel");
   IMM("postidx_imm8");
+  IMM("postidx_imm8s4");
 
   MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
   MISC("uncondbrtarget", "kOperandTypeARMBranchTarget");           // ?
-- 
2.34.1