From 101c5b096fa034c43c508c0b2906680410e36155 Mon Sep 17 00:00:00 2001 From: Oleg Ranevskyy Date: Thu, 5 Nov 2015 17:50:17 +0000 Subject: [PATCH] [DebugInfo] Fix ARM/AArch64 prologue_end position. Related to D11268. Summary: This review is related to another review request http://reviews.llvm.org/D11268, does the same and merely fixes a couple of issues with it. D11268 is quite old and has merge conflicts against the current trunk. This request - rebases D11268 onto the new trunk; - resolves the merge conflicts; - fixes the prologue_end tests, which do not pass due to the subprogram definitions not marked as distinct. Reviewers: echristo, rengolin, kubabrecka Subscribers: aemerson, rengolin, jyknight, dsanders, llvm-commits, asl Differential Revision: http://reviews.llvm.org/D14338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252177 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64FrameLowering.cpp | 32 +++++++------- lib/Target/ARM/ARMFrameLowering.cpp | 31 +++++++------- lib/Target/ARM/Thumb1FrameLowering.cpp | 46 ++++++++++----------- lib/Target/Mips/Mips16FrameLowering.cpp | 18 ++++---- lib/Target/Mips/Mips16ISelDAGToDAG.cpp | 14 +++---- lib/Target/Mips/Mips16InstrInfo.cpp | 42 +++++++++---------- lib/Target/Sparc/SparcFrameLowering.cpp | 18 ++++---- lib/Target/SystemZ/SystemZFrameLowering.cpp | 31 +++++++------- lib/Target/X86/X86FrameLowering.cpp | 15 ++++--- test/DebugInfo/AArch64/prologue_end.ll | 43 +++++++++++++++++++ test/DebugInfo/ARM/prologue_end.ll | 46 +++++++++++++++++++++ test/DebugInfo/Sparc/prologue_end.ll | 41 ++++++++++++++++++ test/DebugInfo/SystemZ/prologue_end.ll | 42 +++++++++++++++++++ 13 files changed, 303 insertions(+), 116 deletions(-) create mode 100644 test/DebugInfo/AArch64/prologue_end.ll create mode 100644 test/DebugInfo/ARM/prologue_end.ll create mode 100644 test/DebugInfo/Sparc/prologue_end.ll create mode 100644 test/DebugInfo/SystemZ/prologue_end.ll diff --git a/lib/Target/AArch64/AArch64FrameLowering.cpp b/lib/Target/AArch64/AArch64FrameLowering.cpp index cd5821f081c..6ccb959239e 100644 --- a/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -284,13 +284,16 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF, MF.getSubtarget().getRegisterInfo()); const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); MachineModuleInfo &MMI = MF.getMMI(); - AArch64FunctionInfo *AFI = MF.getInfo(); - bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry(); - bool HasFP = hasFP(MF); - DebugLoc DL = MBB.findDebugLoc(MBBI); - - // All calls are tail calls in GHC calling conv, and functions have no - // prologue/epilogue. + AArch64FunctionInfo *AFI = MF.getInfo(); + bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry(); + bool HasFP = hasFP(MF); + + // Debug location must be unknown since the first debug location is used + // to determine the end of the prologue. + DebugLoc DL; + + // All calls are tail calls in GHC calling conv, and functions have no + // prologue/epilogue. if (MF.getFunction()->getCallingConv() == CallingConv::GHC) return; @@ -727,15 +730,12 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( MachineFunction &MF = *MBB.getParent(); const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned Count = CSI.size(); - DebugLoc DL; - assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!"); - - if (MI != MBB.end()) - DL = MI->getDebugLoc(); - - for (unsigned i = 0; i < Count; i += 2) { - unsigned idx = Count - i - 2; - unsigned Reg1 = CSI[idx].getReg(); + DebugLoc DL; + assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!"); + + for (unsigned i = 0; i < Count; i += 2) { + unsigned idx = Count - i - 2; + unsigned Reg1 = CSI[idx].getReg(); unsigned Reg2 = CSI[idx + 1].getReg(); // GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI // list to come in sorted by frame index so that we can issue the store diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp index 966f0310f0b..98655203a4f 100644 --- a/lib/Target/ARM/ARMFrameLowering.cpp +++ b/lib/Target/ARM/ARMFrameLowering.cpp @@ -302,13 +302,17 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF, "This emitPrologue does not support Thumb1!"); bool isARM = !AFI->isThumbFunction(); unsigned Align = STI.getFrameLowering()->getStackAlignment(); - unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); - unsigned NumBytes = MFI->getStackSize(); - const std::vector &CSI = MFI->getCalleeSavedInfo(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - unsigned FramePtr = RegInfo->getFrameRegister(MF); - - // Determine the sizes of each callee-save spill areas and record which frame + unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); + unsigned NumBytes = MFI->getStackSize(); + const std::vector &CSI = MFI->getCalleeSavedInfo(); + + // Debug location must be unknown since the first debug location is used + // to determine the end of the prologue. + DebugLoc dl; + + unsigned FramePtr = RegInfo->getFrameRegister(MF); + + // Determine the sizes of each callee-save spill areas and record which frame // belongs to which callee-save spill areas. unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; int FramePtrSpillFI = 0; @@ -890,13 +894,12 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, unsigned NumAlignedDPRCS2Regs, unsigned MIFlags) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); - - DebugLoc DL; - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - SmallVector, 4> Regs; - unsigned i = CSI.size(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + + DebugLoc DL; + + SmallVector, 4> Regs; + unsigned i = CSI.size(); while (i != 0) { unsigned LastReg = 0; for (; i != 0; --i) { diff --git a/lib/Target/ARM/Thumb1FrameLowering.cpp b/lib/Target/ARM/Thumb1FrameLowering.cpp index 6ee5bb82d1c..791e0acbe26 100644 --- a/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -97,13 +97,17 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF, unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); unsigned NumBytes = MFI->getStackSize(); - assert(NumBytes >= ArgRegsSaveSize && - "ArgRegsSaveSize is included in NumBytes"); - const std::vector &CSI = MFI->getCalleeSavedInfo(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - unsigned FramePtr = RegInfo->getFrameRegister(MF); - unsigned BasePtr = RegInfo->getBaseRegister(); - int CFAOffset = 0; + assert(NumBytes >= ArgRegsSaveSize && + "ArgRegsSaveSize is included in NumBytes"); + const std::vector &CSI = MFI->getCalleeSavedInfo(); + + // Debug location must be unknown since the first debug location is used + // to determine the end of the prologue. + DebugLoc dl; + + unsigned FramePtr = RegInfo->getFrameRegister(MF); + unsigned BasePtr = RegInfo->getBaseRegister(); + int CFAOffset = 0; // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. NumBytes = (NumBytes + 3) & ~3; @@ -165,14 +169,12 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF, DPRCSSize += 8; } } - - if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { - ++MBBI; - if (MBBI != MBB.end()) - dl = MBBI->getDebugLoc(); - } - - // Determine starting offsets of spill areas. + + if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { + ++MBBI; + } + + // Determine starting offsets of spill areas. unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize); unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; @@ -543,14 +545,12 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, if (CSI.empty()) return false; - DebugLoc DL; - const TargetInstrInfo &TII = *STI.getInstrInfo(); - - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); - AddDefaultPred(MIB); - for (unsigned i = CSI.size(); i != 0; --i) { + DebugLoc DL; + const TargetInstrInfo &TII = *STI.getInstrInfo(); + + MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); + AddDefaultPred(MIB); + for (unsigned i = CSI.size(); i != 0; --i) { unsigned Reg = CSI[i-1].getReg(); bool isKill = true; diff --git a/lib/Target/Mips/Mips16FrameLowering.cpp b/lib/Target/Mips/Mips16FrameLowering.cpp index 71c2bdba2f9..7994c61fcdd 100644 --- a/lib/Target/Mips/Mips16FrameLowering.cpp +++ b/lib/Target/Mips/Mips16FrameLowering.cpp @@ -36,13 +36,17 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); MachineFrameInfo *MFI = MF.getFrameInfo(); - const Mips16InstrInfo &TII = - *static_cast(STI.getInstrInfo()); - MachineBasicBlock::iterator MBBI = MBB.begin(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - uint64_t StackSize = MFI->getStackSize(); - - // No need to allocate space on the stack. + const Mips16InstrInfo &TII = + *static_cast(STI.getInstrInfo()); + MachineBasicBlock::iterator MBBI = MBB.begin(); + + // Debug location must be unknown since the first debug location is used + // to determine the end of the prologue. + DebugLoc dl; + + uint64_t StackSize = MFI->getStackSize(); + + // No need to allocate space on the stack. if (StackSize == 0 && !MFI->adjustsStack()) return; MachineModuleInfo &MMI = MF.getMMI(); diff --git a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index bce2c1eb448..f471464b904 100644 --- a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -70,13 +70,13 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { return; MachineBasicBlock &MBB = MF.front(); - MachineBasicBlock::iterator I = MBB.begin(); - MachineRegisterInfo &RegInfo = MF.getRegInfo(); - const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); - DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); - unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); - const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; - + MachineBasicBlock::iterator I = MBB.begin(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); + DebugLoc DL; + unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); + const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; + V0 = RegInfo.createVirtualRegister(RC); V1 = RegInfo.createVirtualRegister(RC); V2 = RegInfo.createVirtualRegister(RC); diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index a49572efdbf..c7c87d38db9 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -193,13 +193,13 @@ static void addSaveRestoreRegs(MachineInstrBuilder &MIB, } } // Adjust SP by FrameSize bytes. Save RA, S0, S1 -void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const { - DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); - MachineFunction &MF = *MBB.getParent(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - const BitVector Reserved = RI.getReservedRegs(MF); +void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + DebugLoc DL; + MachineFunction &MF = *MBB.getParent(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + const BitVector Reserved = RI.getReservedRegs(MF); bool SaveS2 = Reserved[Mips::S2]; MachineInstrBuilder MIB; unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; @@ -260,13 +260,13 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, // This is clearly safe at prologue and epilogue. // void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned Reg1, unsigned Reg2) const { - DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); - // - // li reg1, constant - // move reg2, sp + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned Reg1, unsigned Reg2) const { + DebugLoc DL; + // + // li reg1, constant + // move reg2, sp // add reg1, reg1, reg2 // move sp, reg1 // @@ -443,13 +443,13 @@ const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const { else return get(Mips::AddiuSpImmX16); } - -void Mips16InstrInfo::BuildAddiuSpImm - (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const { - DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); - BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm); -} - + +void Mips16InstrInfo::BuildAddiuSpImm + (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const { + DebugLoc DL; + BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm); +} + const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) { return new Mips16InstrInfo(STI); } diff --git a/lib/Target/Sparc/SparcFrameLowering.cpp b/lib/Target/Sparc/SparcFrameLowering.cpp index b92450962f0..a9d22ccdae3 100644 --- a/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/lib/Target/Sparc/SparcFrameLowering.cpp @@ -41,13 +41,13 @@ void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int NumBytes, - unsigned ADDrr, - unsigned ADDri) const { - - DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc(); - const SparcInstrInfo &TII = - *static_cast(MF.getSubtarget().getInstrInfo()); - + unsigned ADDrr, + unsigned ADDri) const { + + DebugLoc dl; + const SparcInstrInfo &TII = + *static_cast(MF.getSubtarget().getInstrInfo()); + if (NumBytes >= -4096 && NumBytes < 4096) { BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) .addReg(SP::O6).addImm(NumBytes); @@ -93,7 +93,9 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF, const SparcRegisterInfo &RegInfo = *static_cast(MF.getSubtarget().getRegisterInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + // Debug location must be unknown since the first debug location is used + // to determine the end of the prologue. + DebugLoc dl; bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); // FIXME: unfortunately, returning false from canRealignStack diff --git a/lib/Target/SystemZ/SystemZFrameLowering.cpp b/lib/Target/SystemZ/SystemZFrameLowering.cpp index 12c4310b78f..940ea117852 100644 --- a/lib/Target/SystemZ/SystemZFrameLowering.cpp +++ b/lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -130,13 +130,13 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, return false; MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); - SystemZMachineFunctionInfo *ZFI = MF.getInfo(); - bool IsVarArg = MF.getFunction()->isVarArg(); - DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - // Scan the call-saved GPRs and find the bounds of the register spill area. - unsigned LowGPR = 0; + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); + SystemZMachineFunctionInfo *ZFI = MF.getInfo(); + bool IsVarArg = MF.getFunction()->isVarArg(); + DebugLoc DL; + + // Scan the call-saved GPRs and find the bounds of the register spill area. + unsigned LowGPR = 0; unsigned HighGPR = SystemZ::R15D; unsigned StartOffset = -1U; for (unsigned I = 0, E = CSI.size(); I != E; ++I) { @@ -319,13 +319,16 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF, SystemZMachineFunctionInfo *ZFI = MF.getInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); - const std::vector &CSI = MFFrame->getCalleeSavedInfo(); - bool HasFP = hasFP(MF); - DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - // The current offset of the stack pointer from the CFA. - int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP; + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const std::vector &CSI = MFFrame->getCalleeSavedInfo(); + bool HasFP = hasFP(MF); + + // Debug location must be unknown since the first debug location is used + // to determine the end of the prologue. + DebugLoc DL; + + // The current offset of the stack pointer from the CFA. + int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP; if (ZFI->getLowSavedGPR()) { // Skip over the GPR saves. diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index ae4cc77fcc9..be6cec6fa59 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -637,12 +637,15 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF, unsigned FramePtr = TRI->getFrameRegister(MF); const unsigned MachineFramePtr = STI.isTarget64BitILP32() - ? getX86SubSuperRegister(FramePtr, MVT::i64, false) - : FramePtr; - unsigned BasePtr = TRI->getBaseRegister(); - DebugLoc DL; - - // Add RETADDR move area to callee saved frame size. + ? getX86SubSuperRegister(FramePtr, MVT::i64, false) + : FramePtr; + unsigned BasePtr = TRI->getBaseRegister(); + + // Debug location must be unknown since the first debug location is used + // to determine the end of the prologue. + DebugLoc DL; + + // Add RETADDR move area to callee saved frame size. int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); if (TailCallReturnAddrDelta && IsWin64Prologue) report_fatal_error("Can't handle guaranteed tail call under win64 yet"); diff --git a/test/DebugInfo/AArch64/prologue_end.ll b/test/DebugInfo/AArch64/prologue_end.ll new file mode 100644 index 00000000000..4887fb06099 --- /dev/null +++ b/test/DebugInfo/AArch64/prologue_end.ll @@ -0,0 +1,43 @@ +; RUN: llc -disable-fp-elim -O0 %s -mtriple aarch64-apple-darwin -o - | FileCheck %s + +; int func(void); +; void prologue_end_test() { +; func(); +; func(); +; } + +define void @prologue_end_test() nounwind uwtable { + ; CHECK: prologue_end_test: + ; CHECK: .cfi_startproc + ; CHECK: stp x29, x30 + ; CHECK: mov x29, sp + ; CHECK: sub sp, sp + ; CHECK: .loc 1 3 3 prologue_end + ; CHECK: bl _func + ; CHECK: bl _func +entry: + %call = call i32 @func(), !dbg !11 + %call1 = call i32 @func(), !dbg !12 + ret void, !dbg !13 +} + +declare i32 @func() + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8, !9} +!llvm.ident = !{!10} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 242129)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3) +!1 = !DIFile(filename: "foo.c", directory: "/tmp") +!2 = !{} +!3 = !{!4} +!4 = distinct !DISubprogram(name: "prologue_end_test", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @prologue_end_test, variables: !2) +!5 = !DISubroutineType(types: !6) +!6 = !{null} +!7 = !{i32 2, !"Dwarf Version", i32 2} +!8 = !{i32 2, !"Debug Info Version", i32 3} +!9 = !{i32 1, !"PIC Level", i32 2} +!10 = !{!"clang version 3.7.0 (trunk 242129)"} +!11 = !DILocation(line: 3, column: 3, scope: !4) +!12 = !DILocation(line: 4, column: 3, scope: !4) +!13 = !DILocation(line: 5, column: 1, scope: !4) diff --git a/test/DebugInfo/ARM/prologue_end.ll b/test/DebugInfo/ARM/prologue_end.ll new file mode 100644 index 00000000000..16a594b13c7 --- /dev/null +++ b/test/DebugInfo/ARM/prologue_end.ll @@ -0,0 +1,46 @@ +; RUN: llc -disable-fp-elim -O0 %s -mtriple armv7-apple-darwin -o - | FileCheck %s +; RUN: llc -disable-fp-elim -O0 %s -mtriple thumbv1-apple-darwin -o - | FileCheck %s + +; int func(void); +; void prologue_end_test() { +; func(); +; func(); +; } + +define void @prologue_end_test() nounwind uwtable { + ; CHECK: prologue_end_test: + ; CHECK: .cfi_startproc + ; CHECK: push {r7, lr} + ; CHECK: {{mov r7, sp|add r7, sp}} + ; CHECK: sub sp + ; CHECK: .loc 1 3 3 prologue_end + ; CHECK: bl {{_func|Ltmp}} + ; CHECK: bl {{_func|Ltmp}} +entry: + %call = call i32 @func(), !dbg !13 + %call1 = call i32 @func(), !dbg !14 + ret void, !dbg !15 +} + +declare i32 @func() + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8, !9, !10, !11} +!llvm.ident = !{!12} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 242129)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3) +!1 = !DIFile(filename: "foo.c", directory: "/tmp") +!2 = !{} +!3 = !{!4} +!4 = distinct !DISubprogram(name: "prologue_end_test", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @prologue_end_test, variables: !2) +!5 = !DISubroutineType(types: !6) +!6 = !{null} +!7 = !{i32 2, !"Dwarf Version", i32 2} +!8 = !{i32 2, !"Debug Info Version", i32 3} +!9 = !{i32 1, !"wchar_size", i32 4} +!10 = !{i32 1, !"min_enum_size", i32 4} +!11 = !{i32 1, !"PIC Level", i32 2} +!12 = !{!"clang version 3.7.0 (trunk 242129)"} +!13 = !DILocation(line: 3, column: 3, scope: !4) +!14 = !DILocation(line: 4, column: 3, scope: !4) +!15 = !DILocation(line: 5, column: 1, scope: !4) diff --git a/test/DebugInfo/Sparc/prologue_end.ll b/test/DebugInfo/Sparc/prologue_end.ll new file mode 100644 index 00000000000..ce73b366927 --- /dev/null +++ b/test/DebugInfo/Sparc/prologue_end.ll @@ -0,0 +1,41 @@ +; RUN: llc -disable-fp-elim -O0 %s -mtriple sparc -o - | FileCheck %s + +; int func(void); +; void prologue_end_test() { +; func(); +; func(); +; } + +define void @prologue_end_test() nounwind uwtable { + ; CHECK: prologue_end_test: + ; CHECK: .cfi_startproc + ; CHECK: save %sp + ; CHECK: .loc 1 3 3 prologue_end + ; CHECK: call func + ; CHECK: call func +entry: + %call = call i32 @func(), !dbg !11 + %call1 = call i32 @func(), !dbg !12 + ret void, !dbg !13 +} + +declare i32 @func() + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8, !9} +!llvm.ident = !{!10} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 242129)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3) +!1 = !DIFile(filename: "foo.c", directory: "/tmp") +!2 = !{} +!3 = !{!4} +!4 = distinct !DISubprogram(name: "prologue_end_test", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @prologue_end_test, variables: !2) +!5 = !DISubroutineType(types: !6) +!6 = !{null} +!7 = !{i32 2, !"Dwarf Version", i32 2} +!8 = !{i32 2, !"Debug Info Version", i32 3} +!9 = !{i32 1, !"PIC Level", i32 2} +!10 = !{!"clang version 3.7.0 (trunk 242129)"} +!11 = !DILocation(line: 3, column: 3, scope: !4) +!12 = !DILocation(line: 4, column: 3, scope: !4) +!13 = !DILocation(line: 5, column: 1, scope: !4) diff --git a/test/DebugInfo/SystemZ/prologue_end.ll b/test/DebugInfo/SystemZ/prologue_end.ll new file mode 100644 index 00000000000..cb71dcff55c --- /dev/null +++ b/test/DebugInfo/SystemZ/prologue_end.ll @@ -0,0 +1,42 @@ +; RUN: llc -disable-fp-elim -O0 %s -mtriple s390x-linux-gnu -o - | FileCheck %s + +; int func(void); +; void prologue_end_test() { +; func(); +; func(); +; } + +define void @prologue_end_test() nounwind uwtable { + ; CHECK: prologue_end_test: + ; CHECK: .cfi_startproc + ; CHECK: aghi + ; CHECK: lgr + ; CHECK: .loc 1 3 3 prologue_end + ; CHECK: brasl {{.*}}, func + ; CHECK: brasl {{.*}}, func +entry: + %call = call i32 @func(), !dbg !11 + %call1 = call i32 @func(), !dbg !12 + ret void, !dbg !13 +} + +declare i32 @func() + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8, !9} +!llvm.ident = !{!10} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 242129)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3) +!1 = !DIFile(filename: "foo.c", directory: "/tmp") +!2 = !{} +!3 = !{!4} +!4 = distinct !DISubprogram(name: "prologue_end_test", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @prologue_end_test, variables: !2) +!5 = !DISubroutineType(types: !6) +!6 = !{null} +!7 = !{i32 2, !"Dwarf Version", i32 2} +!8 = !{i32 2, !"Debug Info Version", i32 3} +!9 = !{i32 1, !"PIC Level", i32 2} +!10 = !{!"clang version 3.7.0 (trunk 242129)"} +!11 = !DILocation(line: 3, column: 3, scope: !4) +!12 = !DILocation(line: 4, column: 3, scope: !4) +!13 = !DILocation(line: 5, column: 1, scope: !4) -- 2.34.1