From 0bb38df86c72e8db5a305cce622c4a559e395bfb Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 24 Sep 2014 02:14:26 +0000 Subject: [PATCH] R600/SI: Fix weird CHECK-DAG usage This prevents these from failing in a future commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218356 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll | 4 ++-- test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll b/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll index c8c73573e07..d0eeeab09c5 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll @@ -6,9 +6,9 @@ declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readn ; SI-LABEL: @test_div_fixup_f32: ; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: S_LOAD_DWORD [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]] ; SI-DAG: S_LOAD_DWORD [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]] +; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]] +; SI-DAG: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]] ; SI: V_DIV_FIXUP_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] ; SI: BUFFER_STORE_DWORD [[RESULT]], ; SI: S_ENDPGM diff --git a/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll b/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll index 4f1e827c2cb..40b441df86b 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll @@ -6,9 +6,9 @@ declare double @llvm.AMDGPU.div.fmas.f64(double, double, double) nounwind readno ; SI-LABEL: @test_div_fmas_f32: ; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: S_LOAD_DWORD [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]] ; SI-DAG: S_LOAD_DWORD [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]] +; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]] +; SI-DAG: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]] ; SI: V_DIV_FMAS_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] ; SI: BUFFER_STORE_DWORD [[RESULT]], ; SI: S_ENDPGM -- 2.34.1