From 08abda6dfa15406333b347cddff3cdca36260df8 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Thu, 22 Oct 2015 18:07:38 +0000 Subject: [PATCH] AArch64: Disable the latency heuristic It turned out not to improve any of our benchmarks but occasionally led to increased register pressure and spilling. Only enabling for the Cyclone CPU as the results on the cortex CPUs give mixed results. Differential Revision: http://reviews.llvm.org/D13708 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251038 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64Subtarget.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/Target/AArch64/AArch64Subtarget.cpp b/lib/Target/AArch64/AArch64Subtarget.cpp index 6dfa0af4f88..e6ef6dc80e2 100644 --- a/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/lib/Target/AArch64/AArch64Subtarget.cpp @@ -114,6 +114,11 @@ void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, // bi-directional scheduling. 253.perlbmk. Policy.OnlyTopDown = false; Policy.OnlyBottomUp = false; + // Enabling or Disabling the latency heuristic is a close call: It seems to + // help nearly no benchmark on out-of-order architectures, on the other hand + // it regresses register pressure on a few benchmarking. + if (isCyclone()) + Policy.DisableLatencyHeuristic = true; } bool AArch64Subtarget::enableEarlyIfConversion() const { -- 2.34.1